axi4

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Here are 15 public repositories matching this topic...

pulp-platform / axi

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AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

asic fpga hardware rtl ip systemverilog axi network-on-chip axi4 axi4-lite

Updated Nov 25, 2024
SystemVerilog

chipsalliance / Cores-VeeR-EH1

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VeeR EH1 core

fpga processor riscv rtl risc risc-v open-source-hardware fusesoc verilator riscv32 western-digital axi4 ahb-lite asic-design veer

Updated May 29, 2023
SystemVerilog

taichi-ishitani / tvip-axi

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AMBA AXI VIP

vip systemverilog uvm axi amba axi4 amba-axi

Updated Jun 28, 2024
SystemVerilog

chipsalliance / Cores-VeeR-EL2

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VeeR EL2 Core

fpga processor riscv rtl risc-v open-source-hardware fusesoc verilator riscv32 western-digital axi4 ahb-lite asic-design el2

Updated Nov 25, 2024
SystemVerilog

taichi-ishitani / tnoc

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Network on Chip Implementation written in SytemVerilog

systemverilog uvm noc axi amba network-on-chip axi4 amba-axi

Updated Aug 27, 2022
SystemVerilog

aignacio / ravenoc

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RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications

router mpsoc noc network-on-chip axi4 flits virtual-channels

Updated Nov 18, 2024
SystemVerilog

loykylewong / FPGA-Application-Development-and-Simulation

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《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS).

Updated Oct 18, 2024
SystemVerilog

dpretet / axi-crossbar

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An AXI4 crossbar implementation in SystemVerilog

arm asic fpga processor riscv verilog soc fpga-soc interconnect amba crossbar riscv32 axi4 axi4-lite riscv64 monodraw axi4-protocol asic-design axi4-full

Updated Nov 21, 2024
SystemVerilog

mmxsrup / axi4-interface

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AXI4 and AXI4-Lite interface definitions

fpga systemverilog axi4 axi4-lite axi4-stream

Updated Sep 20, 2020
SystemVerilog

dpretet / friscv

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RISCV CPU implementation in SystemVerilog

asic fpga assembler riscv verilog systemverilog fpga-soc risc-v rv32i crossbar axi4 axi4-protocol asic-design riscv-cpu

Updated Oct 8, 2024
SystemVerilog

dpretet / meduram

Sponsor

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Multi-port BRAM IP for ASIC and FPGA

block asic fpga ram yosys iverilog fusesoc bram amba axi4 axi4-lite multi-port svut axi4-lite-interface

Updated Apr 21, 2021
SystemVerilog

rggen / rggen-sv-rtl

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Common SystemVerilog RTL modules for RgGen

rtl systemverilog axi apb axi4

Updated Nov 22, 2024
SystemVerilog

gururavi / rtl

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Synchronous and Asynchronous FIFO with AXI interface

fpga pipeline rtl synthesis systemverilog fifo axi floating-point-arithmetic axi-stream axi4

Updated Nov 20, 2019
SystemVerilog

muhammadtalhasami / Axi4_lite_interface

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This repo contains an implementation of Axi4 lite interface on system verilog. Verilator and Vivado tools are used .

vivado system-verilog verilator axi4 axi4-lite axi4-protocol axi4-lite-interface axi4-lite-system-verilog

Updated May 4, 2024
SystemVerilog

vbogdev / vbn-Riscv

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An attempt at making a 2-way superscalar out-of-order riscv processor for an Arty s25 fpga.

processor-architecture fpga processor out-of-order superscalar risc-v processor-simulator ddr3 processor-design axi4 superscalar-cpu

Updated Oct 7, 2024
SystemVerilog

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axi4

Here are 15 public repositories matching this topic...

pulp-platform / axi

chipsalliance / Cores-VeeR-EH1

taichi-ishitani / tvip-axi

chipsalliance / Cores-VeeR-EL2

taichi-ishitani / tnoc

aignacio / ravenoc

loykylewong / FPGA-Application-Development-and-Simulation

dpretet / axi-crossbar

mmxsrup / axi4-interface

dpretet / friscv

dpretet / meduram

rggen / rggen-sv-rtl

gururavi / rtl

muhammadtalhasami / Axi4_lite_interface

vbogdev / vbn-Riscv

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