PaddlePaddle High Performance Deep Learning Inference Engine for Mobile and Edge (飞桨高性能深度学习端侧推理引擎）

Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pipelines.

Machine learning on FPGAs using HLS

Universal utility for programming FPGA

Verilog to Routing -- Open Source CAD Flow for FPGA Research

Samples for Intel® oneAPI Toolkits

Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)

A lightweight high performance tensor algebra framework for modern C++

This project accelerates CNN computation with the help of FPGA, for more than 50x speed-up compared with CPU.

HAL – The Hardware Analyzer

Run Time for AIE and FPGA based platforms

KiwiSDR: BeagleBone web-accessible shortwave receiver and software-defined GPS (archived)

Generic system-wide modern C++ for heterogeneous platforms with SYCL from Khronos Group

A Just-In-Time Compiler for Verilog from VMware Research

80186 compatible SystemVerilog CPU core and FPGA reference design

SDAccel Examples

Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.

A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.

Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4

PandA-bambu public repository