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synthesizable

Here are 4 public repositories matching this topic...

sgherbst / svreal

Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats

simulation verilog vcs synthesis vivado systemverilog fixed-point floating-point icarus-verilog iverilog icarus verilator xrun synthesizable xcelium irun ncsim

Updated Jan 13, 2021
SystemVerilog

sgherbst / msdsl

Automatic generation of real number models from analog circuits

python generator simulation analog model synthesis rnm mixed-signal ams synthesizable analog-circuits real-number-modeling

Updated Apr 2, 2024
Python

SnrNotHere16 / Asynchronous-FIFO

An FPGA implementation of Cummings' Asynchronous FIFO

Updated Apr 14, 2022
SystemVerilog

erictaur / Component-Labeler

A hardware implementation of component labeling

verilog synthesizable component-labeler

Updated Jan 13, 2021
Verilog

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