SublimeLinter plugin for linting Verilog and SystemVerilog with Modelsim vlog
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Updated
Dec 21, 2017 - Python
SublimeLinter plugin for linting Verilog and SystemVerilog with Modelsim vlog
⚡👌 ModelSim vcom/vlog plugin for SublimeLinter. Linting for VHDL and Verilog/SystemVerilog.
Atom-linter provider that runs vcs and parses output. This can be used as a systemverilog (/verilog/vhdl) linter.
Provides a packaged collection of open source EDA tools
Python/Simulator integration using procedure calls
CoreIR Symbolic Analyzer
GUI based UVM Test Environment generation tool
Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.
Python library for parsing module definitions and instantiations from SystemVerilog files
Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)
SystemVerilog & Verilog Module I/O parser and printer
Vim plugin to work easier with Verilog & SystemVerilog
A SystemRDL 2.0 to (synthesizable) SystemVerilog compiler.
This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI workflow.
🪀 Tool to play with HDL (inspired by EdaPlayground)
Vivado Simulator (XSim) xvlog/xvhdl plugin for SublimeLinter. Linting for Verilog/SystemVerilog and VHDL.
Open source RTL simulation acceleration on commodity hardware
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