An antidote to remove wildcard I/O instantiations from Verilog and SystemVerilog files.
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Updated
Aug 8, 2024 - Python
An antidote to remove wildcard I/O instantiations from Verilog and SystemVerilog files.
Making cocotb testbenches that bit easier
A flexible and scalable development platform for modern FPGA projects.
A Python-based tool for generating Verilog modules with features including customizable state machines, port definitions, and state diagrams using Graphviz. Ideal for FPGA and ASIC design workflows.
pulp_soc is the core building component of PULP based SoCs
GitHub Action to install Orbit
Packed data structure specifications for multi-language hardware projects.
An abstraction library for interfacing EDA tools
SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
LLVM based HLS library for HWToolkit (hardware devel. toolkit)
Translates IPXACT XML to synthesizable VHDL or SystemVerilog
Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
Repurposing existing HDL tools to help writing better code
Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
An opinionated build environment for EDA projects
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
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