AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
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Updated
Jul 31, 2024 - SystemVerilog
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Functional verification project for the CORE-V family of RISC-V cores.
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
An abstraction library for interfacing EDA tools
FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器,用于驱动BLDC/PMSM电机。
Haskell to VHDL/Verilog/SystemVerilog compiler
SystemVerilog compiler and language services
NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
pulp_soc is the core building component of PULP based SoCs
HDL support for VS Code
Test suite designed to check compliance with the SystemVerilog standard.
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
An FPGA-based lightweight CAN bus controller. 基于FPGA的轻量级CAN总线控制器。
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