Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.

Example designs showing different ways to use F4PGA toolchains.

VexRiscV system with GDB-Server in Hardware

A toy L4 load balancer running on FPGA

Briey SoC on ECP5 (ICESugar Pro)

Briey SoC on Sipeed Tang Primer

Yet another faux-retro game system

A small framework to simplify the creation of custom instruction for the VexRiscv.

Co-architect 32-bit open-source RISC-V soft-cores for improved FPGA implementations

Source files and notes of my Final Year Project, as part of an MEng in Electronics and Information Engineering from Imperial College London