soc.py: SoCRegion: add CTOR param to bypass address decoding, SoC: ad…

…d attribute to bypass CSR decoding and use it add_csr_bridge

litex/soc/integration/soc.py

@@ -59,28 +59,30 @@ def SoCConstant(value):
 # SoCRegion ----------------------------------------------------------------------------------------
 
 class SoCRegion:
-    def __init__(self, origin=None, size=None, mode="rw", cached=True, linker=False):
-        self.logger    = logging.getLogger("SoCRegion")
-        self.origin    = origin
-        self.size      = size
+    def __init__(self, origin=None, size=None, mode="rw", cached=True, linker=False, bypass_decoder=False):
+        self.logger         = logging.getLogger("SoCRegion")
+        self.origin         = origin
+        self.bypass_decoder = bypass_decoder
+        self.size           = size
         if size != 2**log2_int(size, False):
             self.logger.info("Region size {} internally from {} to {}.".format(
                 colorer("rounded", color="cyan"),
                 colorer("0x{:08x}".format(size)),
                 colorer("0x{:08x}".format(2**log2_int(size, False)))))
-        self.size_pow2 = 2**log2_int(size, False)
-        self.mode      = mode
-        self.cached    = cached
-        self.linker    = linker
+        self.size_pow2      = 2**log2_int(size, False)
+        self.mode           = mode
+        self.cached         = cached
+        self.linker         = linker
 
     def decoder(self, bus):
         origin = self.origin
+
         size   = self.size_pow2
         if (origin & (size - 1)) != 0:
             self.logger.error("Origin needs to be aligned on size:")
             self.logger.error(self)
             raise SoCError()
-        if (origin == 0) and (size == 2**bus.address_width):
+        if (origin == 0) and (size == 2**bus.address_width) or self.bypass_decoder:
             return lambda a: True
         origin >>= int(log2(bus.data_width//8)) # bytes to words aligned.
         size   >>= int(log2(bus.data_width//8)) # bytes to words aligned.
@@ -747,6 +749,7 @@ def __init__(self, platform, sys_clk_freq,
         self.sys_clk_freq = sys_clk_freq
         self.constants    = {}
         self.csr_regions  = {}
+        self.csr_decode_bypass = False,
 
         # SoC Bus Handler --------------------------------------------------------------------------
         self.submodules.bus = SoCBusHandler(
@@ -877,7 +880,8 @@ def add_csr_bridge(self, origin, register=False):
                 data_width    = self.csr.data_width),
             register=register)
         csr_size = 2**(self.csr.address_width + 2)
-        csr_region = SoCRegion(origin=origin, size=csr_size, cached=False)
+        csr_region = SoCRegion(origin=origin, size=csr_size, cached=False,
+                               bypass_decoder=self.csr_decode_bypass)
         bus = getattr(self.csr_bridge, self.bus.standard.replace('-', '_'))
         self.bus.add_slave("csr", bus, csr_region)
         self.csr.add_master(name="bridge", master=self.csr_bridge.csr)