Add ID and spiOverJtag bitstream for Stratix V GS D5 #490
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Hi,
I added support for a Stratix V GS D5 FPGA.
Specifically this PR is for the support of the Microsoft Azure Catapult V2 cards named "Pikes Peak" and "Storey Peak". Those cards, which show up cheaply on eBay every now and then, contain a special version of a Stratix V GS D5 with the full model number of
5SGSMD5K1F40C1
and a JTAG device ID of0x029070dd
.The
spiOverJtag
design that I built is for5SGSMD5K2F40I3
which should be the closest match that is not "special" and publicly documented and it works on my FPGA as well. The built bitstream might even work on all Stratix V GS D5 FPGAs, however I have not tested that. Also, to build the bitstream you need at least Quartus Standard. The free Lite version is not enough.I tested the FPGA SRAM write and SPI flash read as follows on a Storey Peak card and got good results:
edit:
Oh, one more thing! I had to patch something in the quarus megafunctions files, because I wasn't able to build designs that use the serial flash loader. I always got the following error message:
Node instance "altclkctrl_component" instantiates undefined entity "altclkctrl_inst".
When googling, I found the following Intel Community forum thread: https://community.intel.com/t5/Programmable-Devices/Error-Message-12006-with-Quartus-Prime-Standard-Edition-23-1/m-p/1572452
The official help wasn't particularly helpful, so I just winged it and patched line 195 in file
quartus/libraries/megafunctions/alt_sfl_enhanced.v
where thisaltclkctrl
block is instantiated fromaltclkctrl_inst altclkctrl_component
toaltclkctrl altclkctrl_inst
and stuff started to work. Just FYI, this seems to be an issue on Intel/Altera's side.All this on Quartus Prime Standard 23.1.