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Add ID and spiOverJtag bitstream for Stratix V GS D5 #490

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merged 1 commit into from
Oct 10, 2024
Merged

Add ID and spiOverJtag bitstream for Stratix V GS D5 #490

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7 changes: 7 additions & 0 deletions doc/FPGAs.yml
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Expand Up @@ -108,6 +108,13 @@ Intel:
URL: https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-v.html
Memory: OK
Flash: NT

- Description: Stratix V GS
Model:
- 5SGSD5
URL: https://www.intel.de/content/www/de/de/products/sku/210318/stratix-v-5sgsd5-fpga/specifications.html
Memory: OK
Flash: OK

- Description: Cyclone 10 LP
Model: 10CL025
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2 changes: 1 addition & 1 deletion spiOverJtag/Makefile
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Expand Up @@ -22,7 +22,7 @@ XILINX_PARTS := xc3s500evq100 \
XILINX_BIT_FILES := $(addsuffix .bit.gz,$(addprefix spiOverJtag_, $(XILINX_PARTS)))

ALTERA_PARTS := 10cl025256 10cl016484 10cl055484 \
ep4ce622 ep4ce1017 ep4ce2217 ep4ce1523 ep4ce11523 ep4cgx15027 5ce215 5ce223 5ce423 5ce523 5ce927
ep4ce622 ep4ce1017 ep4ce2217 ep4ce1523 ep4ce11523 ep4cgx15027 5ce215 5ce223 5ce423 5ce523 5ce927 5sgsd5
ALTERA_BIT_FILES := $(addsuffix .rbf.gz, $(addprefix spiOverJtag_, $(ALTERA_PARTS)))

EFINIX_PARTS := t8f81 t13f256 ti180j484
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2 changes: 2 additions & 0 deletions spiOverJtag/altera_spiOverJtag.v
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Expand Up @@ -19,6 +19,8 @@ module spiOverJtag ();
.INTENDED_DEVICE_FAMILY ("Cyclone IV E"),
`elsif cyclonev
.INTENDED_DEVICE_FAMILY ("Cyclone V"),
`elsif stratixv
.INTENDED_DEVICE_FAMILY ("Stratix V"),
`endif
.ENHANCED_MODE (1),
.ENABLE_SHARED_ACCESS ("ON"),
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8 changes: 7 additions & 1 deletion spiOverJtag/build.py
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Expand Up @@ -32,6 +32,11 @@
tool = "quartus"
files.append({'name': currDir + 'constr_cycloneV.tcl',
'file_type': 'tclSource'})
elif subpart[0:2] == '5s':
family = "Stratix V"
tool = "quartus"
files.append({'name': currDir + 'constr_cycloneV.tcl',
'file_type': 'tclSource'})
elif subpart == "xc7a":
family = "Artix"
tool = "vivado"
Expand Down Expand Up @@ -204,7 +209,8 @@
"5ce423" : "5CEBA4F23C8",
"5ce927" : "5CEBA9F27C7",
"5cse423" : "5CSEMA4U23C6",
"5cse623" : "5CSEBA6U23I7"}[part]
"5cse623" : "5CSEBA6U23I7",
"5sgsd5" : "5SGSMD5K2F40I3"}[part]
files.append({'name': currDir + 'altera_spiOverJtag.v',
'file_type': 'verilogSource'})
files.append({'name': currDir + 'altera_spiOverJtag.sdc',
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Binary file added spiOverJtag/spiOverJtag_5sgsd5.rbf.gz
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3 changes: 3 additions & 0 deletions src/part.hpp
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Expand Up @@ -206,6 +206,9 @@ static std::map <uint32_t, fpga_model> fpga_list = {
{0x020f30dd, {"altera", "cyclone 10 LP", "10CL025", 10}},
{0x020f50dd, {"altera", "cyclone 10 LP", "10CL055", 10}},

/* Altera Stratix V */
{0x029070dd, {"altera", "stratix V GS", "5SGSD5", 10}},

/**************************************************************************/
/* Efinix */
/**************************************************************************/
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