1. Requirements
- Schematic and specification:
2. Design
- Calculate Kn, Kp from library 180nm
With L of PMOS and NMOS are 0.5um
- Find W3, W4
- Find W1, W2
- Find W5
- Find W6
- Find W7 and calculate Av, Pdiss
- Calculate Vbias and Vout(max), Vout(min)
3. Results
- LTSPICE schematic:
- Simulation of Av: Vpp of Vin is 10uV, Vpp of Vout is 56.3mV => Av = 56.3mV / 10uV = 5630 V/V
- Simulation of Gain Bandwidth and Phase Margin: At 0dB have GB = 9.23MHz and PM = 180 - 112 = 68 degree
- Simulation of ICMR: Connect Vout with Vin(-) and simulate in DC mode has ICMR: -0.081V -> 0.333V
- Simulation of Vout range: simulate with DC mode has Vout range: -0.64V -> 0.753V
- Simulation of Slew Rate:
- Simulation of Power Dissipation
Comparision
