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Support FIRRTL2 bridge + Chisel 6 annos for FireSim #2013

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merged 1 commit into from
Aug 22, 2024

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abejgonzalez
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@abejgonzalez abejgonzalez commented Aug 21, 2024

Subsumes #1863.

  • Adds a new generator to FireChip that can generate Chisel3 FIRRTL (only used for FireChip)
  • FireSim now just uses Chisel3/Chisel6 compatible sources
  • Cleanups up as many references to Chisel3 in SBT + Scala sources

Finishes decoupling Chipyard and FireSim!

Related PRs / Issues:

Type of change:

  • Bug fix
  • New feature
  • Other enhancement

Impact:

  • RTL change
  • Software change (RISC-V software)
  • Build system change
  • Other

Contributor Checklist:

  • Did you set main as the base branch?
  • Is this PR's title suitable for inclusion in the changelog and have you added a changelog:<topic> label?
  • Did you state the type-of-change/impact?
  • Did you delete any extraneous prints/debugging code?
  • Did you mark the PR with a changelog: label?
  • (If applicable) Did you update the conda .conda-lock.yml file if you updated the conda requirements file?
  • (If applicable) Did you add documentation for the feature?
  • (If applicable) Did you add a test demonstrating the PR?
  • (If applicable) Did you mark the PR as Please Backport?

@abejgonzalez abejgonzalez self-assigned this Aug 21, 2024
@abejgonzalez abejgonzalez changed the title WIP: For FireSim, support FIRRTL2 bridge + Chisel 6 annos Support FIRRTL2 bridge + Chisel 6 annos for FireSim Aug 22, 2024
@abejgonzalez abejgonzalez changed the base branch from split-v1 to main August 22, 2024 06:02
@abejgonzalez abejgonzalez reopened this Aug 22, 2024
- All targets now compile w/ Chisel6
- Remove Chisel3 references as much as possible
- Add flag --emit-legacy-sfc to run SFC FIRRTL emission
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@jerryz123 jerryz123 left a comment

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Very nice. Thanks for pushing this through.

@abejgonzalez abejgonzalez merged commit 51b66dd into main Aug 22, 2024
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2 participants