[systemverilog] Add keywords

Units/parser-verilog.r/systemverilog-github2635.d/args.ctags

@@ -0,0 +1 @@
+--sort=no

Units/parser-verilog.r/systemverilog-github2635.d/expected.tags

@@ -0,0 +1,18 @@
+ctags_uni_issues	input.sv	/^module ctags_uni_issues ($/;"	m
+data_in	input.sv	/^  input var logic data_in \/\/ var:port, data_in:register => data_in:port$/;"	p	module:ctags_uni_issues
+foo	input.sv	/^  const var foo;$/;"	r	module:ctags_uni_issues
+bar	input.sv	/^  var bar;$/;"	r	module:ctags_uni_issues
+variable_name	input.sv	/^  chandle variable_name ; \/\/ not defined => variable_name:register$/;"	r	module:ctags_uni_issues
+x	input.sv	/^class x;$/;"	C
+ra	input.sv	/^  rand var ra;$/;"	r	class:x
+rb	input.sv	/^  randc var rb;$/;"	r	class:x
+foo	input.sv	/^package foo;$/;"	K
+delay_example	input.sv	/^  sequence delay_example(x, y, min, max, delay1);$/;"	R	package:foo
+x	input.sv	/^  sequence delay_example(x, y, min, max, delay1);$/;"	p	property:foo.delay_example
+y	input.sv	/^  sequence delay_example(x, y, min, max, delay1);$/;"	p	property:foo.delay_example
+min	input.sv	/^  sequence delay_example(x, y, min, max, delay1);$/;"	p	property:foo.delay_example
+max	input.sv	/^  sequence delay_example(x, y, min, max, delay1);$/;"	p	property:foo.delay_example
+delay1	input.sv	/^  sequence delay_example(x, y, min, max, delay1);$/;"	p	property:foo.delay_example
+mh1	input.sv	/^module mh1 ($/;"	m	property:foo.delay_example
+in1	input.sv	/^  input var int in1, \/\/ -> var:port, in1:register => in1:port$/;"	p	module:foo.delay_example.mh1
+out2	input.sv	/^  output var int out2 \/\/ -> var:port, out2:register => out2:port$/;"	p	module:foo.delay_example.mh1

Units/parser-verilog.r/systemverilog-github2635.d/input.sv

@@ -0,0 +1,36 @@
+//
+// from LRM-2017
+//
+module ctags_uni_issues (
+  // 6.8 Variable declarations
+  input var logic data_in // var:port, data_in:register => data_in:port
+);
+
+  const var foo;
+  var bar;
+
+  // 6.14 Chandle data type
+  chandle variable_name ; // not defined => variable_name:register
+endmodule
+
+// 8. Classes
+// 8.3
+class x;
+  rand var ra;
+  randc var rb;
+endclass
+
+package foo;
+  // 16.8 Declaring sequences
+  // sequence is not supported
+  sequence delay_example(x, y, min, max, delay1);
+    x ##delay1 y[*min:max];
+  endsequence
+endpackage
+
+// 23.2 Module definitions
+module mh1 (
+  input var int in1, // -> var:port, in1:register => in1:port
+  output var int out2 // -> var:port, out2:register => out2:port
+);
+endmodule

parsers/verilog.c

@@ -175,7 +175,9 @@ static const keywordAssoc KeywordTable [] = {
 	{ "assume",    K_ASSERTION, { 1, 0 } },
 	{ "bit",       K_REGISTER,  { 1, 0 } },
 	{ "byte",      K_REGISTER,  { 1, 0 } },
+	{ "chandle",   K_REGISTER,  { 1, 0 } },
 	{ "class",     K_CLASS,     { 1, 0 } },
+	{ "const",     K_IGNORE,    { 1, 0 } },
 	{ "cover",     K_ASSERTION, { 1, 0 } },
 	{ "covergroup",K_COVERGROUP,{ 1, 0 } },
 	{ "enum",      K_ENUM,      { 1, 0 } },
@@ -190,7 +192,10 @@ static const keywordAssoc KeywordTable [] = {
 	{ "program",   K_PROGRAM,   { 1, 0 } },
 	{ "property",  K_PROPERTY,  { 1, 0 } },
 	{ "pure",      K_IGNORE,    { 1, 0 } },
+	{ "rand",      K_IGNORE,    { 1, 0 } },
+	{ "randc",     K_IGNORE,    { 1, 0 } },
 	{ "ref",       K_PORT,      { 1, 0 } },
+	{ "sequence",  K_PROPERTY,  { 1, 0 } },
 	{ "shortint",  K_REGISTER,  { 1, 0 } },
 	{ "shortreal", K_REGISTER,  { 1, 0 } },
 	{ "static",    K_IGNORE,    { 1, 0 } },
@@ -201,6 +206,7 @@ static const keywordAssoc KeywordTable [] = {
 	{ "union",     K_STRUCT,    { 1, 0 } },
 	{ "unsigned",  K_IGNORE,    { 1, 0 } },
 	{ "virtual",   K_IGNORE,    { 1, 0 } },
+	{ "var",       K_REGISTER,  { 1, 0 } },
 	{ "void",      K_IGNORE,    { 1, 0 } }
 };