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Verilog: support virtual interface variables #3720

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May 13, 2023
Merged

Verilog: support virtual interface variables #3720

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4d4aad0
Verilog: support virtual interface variables
hirooih May 11, 2023
ebb1bde
Verilog, cosmetic: tabify
hirooih May 13, 2023
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5 changes: 5 additions & 0 deletions Units/parser-verilog.r/systemverilog-interface.d/expected.tags
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Original file line number Diff line number Diff line change
Expand Up @@ -28,3 +28,8 @@ intf_automatic input.sv /^interface automatic intf_automatic;$/;" I
logic_automatic input.sv /^ logic logic_automatic;$/;" r interface:intf_automatic
intf_automatic.logic_automatic input.sv /^ logic logic_automatic;$/;" r interface:intf_automatic
external_interface input.sv /^extern interface external_interface;$/;" Q
ubus_env input.sv /^class ubus_env extends uvm_env;$/;" C
vif input.sv /^ protected virtual interface ubus_if vif;$/;" r class:ubus_env
ubus_env.vif input.sv /^ protected virtual interface ubus_if vif;$/;" r class:ubus_env
has_bus_monitor input.sv /^ protected bit has_bus_monitor = 1;$/;" r class:ubus_env
ubus_env.has_bus_monitor input.sv /^ protected bit has_bus_monitor = 1;$/;" r class:ubus_env
10 changes: 10 additions & 0 deletions Units/parser-verilog.r/systemverilog-interface.d/input.sv
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Expand Up @@ -22,3 +22,13 @@ interface automatic intf_automatic;
endinterface

extern interface external_interface;

// from UVM-1.2
class ubus_env extends uvm_env;

// Virtual Interface variable
protected virtual interface ubus_if vif;

// Control properties
protected bit has_bus_monitor = 1;
endclass : ubus_env
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