Figure 7.1 depicts the datapath for the calculator to be designed in this experiment. The wires in the vertical direction represent the data, while the labeled horizontal wires coming from the sides, including the ALU Carry-In (Cin) signal, are the control signals from the FSM used to facilitate various operations through the calculator. Depending on the Input_Select signal, various externally and internally generated data signals can be fed to the datapath from the top: Bitwise inverted and non-inverted input data (DIN), inverted and non-inverted register B (RB), arithmetic-right-shifted (ARS), logical-right-shifted (LRS), and logical-left-shifted (LLS), and non-shifted register A (RA). Both RA and RB are 4-bit wide. The 4-bit Arithmetic Logic Unit (ALU), ARS, LRS, LLS units are purely combinational, and do not contain any memory elements. The ALU unit in this calculator can only do one of eight operations based on the ALU_OP value, as shown in Table 7.1 below. Note the clock signal going to RA and RB are not shown in Figure 7.1.
- Programming Language: Vhdl
- IDE: Altera Quartus
- Device: DEO Board with Cyclone III EP3C16F484C6 FPGA
FSM stands for Finite State Machine. It is a mathematical model used in computer science and engineering to design and describe the behavior of systems that can be in a finite number of states at any given time. FSMs are widely used in various applications, including digital circuit design, software engineering, natural language processing, and modeling real-world systems
We have 5 states with One-Hot Statement Let me briefly explain what this FSM vhdl code is doing. When Run input is 1 and clock is rising from 0 to 1(rising clock edge) we can change our states like s0,s1,s2, s3, s4, consecutively. It will stay at current state but when Run input becomes 0 then states return to s0. When we defined all micro-operations(MOP) we can control outputs with inputs(Load_A, Load_B, Reset, Cin, Aluop …).
There are 3 inputs MOP, RUN, CLK and according to them output is changing. if we select 0110, ADD21 micro-operation will do, or if we select 0111 ADD3 micro operation will do.
Arithmetic Logic Unit (ALU) is a crucial component within a computer's central processing unit (CPU) that performs arithmetic and logic operations on data. It is responsible for carrying out various mathematical operations like addition, subtraction, multiplication, division, as well as logical operations such as AND, OR, NOT, and comparisons like greater than, less than, and equal to.
I tried to show you every ALU operation 0 to 7 you can select operation then with X and Y which is entered by user it will do operations like addition, and, xor, or etc. For example if you select ALU_OP=001, Cin=0 X =1010 and Y=0011 it will give result of ALU_OUT=1101 or if there is Cin=1 it will give result of ALU_OUT=1110
Arithmetic right shift is a bitwise operation that shifts the bits of a binary number to the right. In this operation, the most significant bit (the leftmost bit, often called the sign bit in signed number representations) is used as the fill bit. When you perform an arithmetic right shift, the sign bit is copied into the vacant bit positions that are created by the shift.
Starting with most significant bit , ARS shifts every bit of 4 - bit output of the RA(RegisterA) to the right by 1,but most significant one stays what it is before.
For example in this one first one is 1000 then with ARS it will become 1100 as you can see from waveform
Logical Right Shift is a bitwise operation that shifts the bits of a binary number to the right. In a logical right shift, vacant positions created by the shift are filled with zeros. Unlike an arithmetic right shift where the sign bit is copied, in a logical right shift, zeros are always used to fill the empty positions. LRS shifts every bit of 4-bit output of the RA(RegisterA) starting with most significant one to right by 1 and most significant bit will be 0
In this one for example if LRS_INPUT=1010 after LRS, LRS_OUTPUT will become 0100
Logical Left Shift is a bitwise operation that shifts the bits of a binary number to the left. In a logical left shift, vacant positions created by the shift are filled with zeros. Each bit in the binary number is moved to the left by a specified number of positions, and zeros are filled in from the right.
This one starts with least significant bit and every bit of 4 bit output of RA(registerA) are shifted by LLS to left by 1 and least significant bit will be 0
As you can see in this one for example if input is 0011 after LLS output will become 0110
8-to-1 multiplexer (often abbreviated as 8x1 MUX) is a combinational circuit that selects one of the 8 input data lines and directs it to a single output line. The selection of the input line to be routed to the output line is controlled by 3 selection lines (A, B, and C in this case) that provide 3 bits of control. Here's how it works:
- Inputs: The multiplexer has 8 input lines (usually labeled D0 to D7), each carrying a binary signal (0 or 1).
- Selection Lines: The 3 selection lines (A, B, and C) determine which input line is selected. These lines can represent any binary number from 000 to 111, where each combination of A, B, and C represents a unique selection.
- Output: The selected input line's value is transferred to the output line (often labeled Y).
The truth table for an 8-to-1 multiplexer is as follows:
In this truth table, D0 to D7 represent the input data lines. The combination of A, B, and C selects one of these lines, and the value on the selected input line is transmitted to the output Y.
8to1 multiplexer is based on 8 inputs each selection input is 3bit. 100 is the fourth input or 010 is second input etc.
In this one for example if I select ınput select as 100 then output will RB directly and RB is [13] => output = [13] || or if I select ınput select as 001(LLS) output will be [7]
In digital electronics, a register is a group of flip-flops (binary storage elements) that store binary data as individual bits. Registers are fundamental building blocks used in various parts of a computer system, including processors, memory units, and input/output interfaces. They are crucial for data manipulation, storage, and transfer within a digital system.
Here are the key aspects of registers:
Storage of Data: Registers store binary data, which can represent numbers, instructions, addresses, or any other digital information. Each bit within a register can store either 0 or 1.
Size: Registers can vary in size, commonly coming in sizes such as 8-bit, 16-bit, 32-bit, or 64-bit, indicating the number of bits they can store. For example, a 32-bit register can store 32 binary digits (bits).
Data Manipulation: Registers are used for various arithmetic and logic operations. Processors use registers to perform computations, comparisons, and other operations, making them essential for the central processing unit (CPU) functionality.
Data Transfer: Data is transferred between registers and other parts of the computer system, such as memory or input/output devices. Registers act as temporary storage during these transfers.
Data Buffering: Registers are used as buffers to hold data temporarily when transferring data between different parts of a system operating at different speeds.
Types of Registers:
- Data Registers: Used to store data temporarily during operations.
- Address Registers: Store memory addresses for read and write operations.
- Program Counter (PC): Holds the memory address of the next instruction to be executed.
- Instruction Register (IR): Stores the current instruction being executed.
- Status Register/Flags Register: Holds status flags (e.g., zero, carry, overflow) indicating the outcome of operations.
- Index Registers: Used for indexing in memory operations.
Whenever clock is on rising edge and if input of load is 1 register takes new Data and stores it however if load=0 it continues to stores same data or if reset is 1 it reset the data which is stored
My first input is [3] until clock is on rising edge, load is 1 and rst is 0 output stays as a [0] when this condition happens my input [3] appears on output. After this when clock is again rising and load is 1 my output should be [3] but there is another factor reset is also 1 when clock is on rising edge so my output appears as [0] which means it resets.
We can see “010” ALU operation which is ADD3 mıcro operation in this waveform which is (cin+loadA+LoadB)
Fmax can be found from 1/T, T is worst case delay and 1/(4.5*10^-9) =0.22x10^9
Now we can run whole 4-bit calculator with all operations we set up for calculator. It have some main parts which are FSM(Finite State Machine) which has MOP(Micro-operations). Datapath that includes calculator's brain which is ALU(Arithmetic Logic Unit), multiplexers and hexadecimal decoder. This project was very important for me because after all logic design related knowledge I learned, now I can see bigger picture after I combine everything I learned. Now I can see that theory turns into practice with my 4-bit FPGA calculator.