Release v0.0.10 · zachjs/sv2v

Added support for assignments within expressions (e.g., x = ++y;)
Added support for excluding the conversion of unbased unsized literals (e.g., '1, 'x) via --exclude UnbasedUniszed
Added support for enumerated type ranges (e.g., enum { X[3:5] })
Added support for complex event expressions (e.g., @(x ^ y))
Added support for the SystemVerilog edge event
Added support for cycle delay ranges in assertion sequence expressions
Added support for procedural continuous assignments (assign/deassign and force/release)
Added conversion for do while loops
Added support for hierarchical calls to functions with no inputs
Added support for passing through DPI imports and exports
Added support for passing through functions with output ports
Extended applicability of simplified Yosys-compatible for loop elaboration

Certain errors raised during conversion now also provide hierarchical and approximate source location information to help locate the error

Fixed inadvertent design behavior changes caused by constant folding removing intentional width-extending operations such as + 0 and * 1
Fixed forced conversion to reg of data sensed in an edge-controlled procedural assignment
always_comb and always_latch now generate explicit sensitivity lists where necessary because of calls to functions which reference non-local data
Fixed signed struct fields being converted to unsigned expressions when accessed directly
Fixed conversion of casts using structs containing multi-dimensional fields
Fixed incorrect name resolution conflicts raised during interface inlining
Fixed handling of interface instances which shadow other declarations
Fixed names like <pkg>_<name> being shadowed by elaborated packages

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