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[Backport v3.7-branch] arch: riscv: reset global pointer on exception #81370

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merged 3 commits into from
Nov 14, 2024

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@zephyrbot zephyrbot commented Nov 14, 2024

Backport 408c151~3..408c151 from #81155.

Fixes #81372

Add macros to read / write hardware registers.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
(cherry picked from commit de3a845)
Reset the gp on exception entry from u-mode to protect the kernel
against a possible rogue user thread.

Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
(cherry picked from commit e30db2d)
Add a test to make sure that the `gp` global pointer register used for
relative addressing when `CONFIG_RISCV_GP` is enabled can't be
corrupted by a rogue user thread.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
(cherry picked from commit 408c151)
@zephyrbot zephyrbot added Backport Backport PR and backport failure issues area: Architectures area: RISCV RISCV Architecture (32-bit & 64-bit) labels Nov 14, 2024
@ycsin ycsin requested review from ceolin and cfriedt November 14, 2024 03:19
@ycsin ycsin added this to the v3.7.1 milestone Nov 14, 2024
@ycsin ycsin added area: Security Security Release Blocker Use this label for justified release blockers labels Nov 14, 2024
@nashif nashif merged commit c1eab82 into v3.7-branch Nov 14, 2024
27 checks passed
@nashif nashif deleted the backport-81155-to-v3.7-branch branch November 14, 2024 21:56
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area: Architectures area: RISCV RISCV Architecture (32-bit & 64-bit) area: Security Security Backport Backport PR and backport failure issues Release Blocker Use this label for justified release blockers
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7 participants