An N-bit synchronous (clocked) counter hardware module with an asynchronous reset written in SystemC, VHDL and SystemVerilog. By default, N is set to 17.
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An N-bit counter module written in SystemC, VHDL and Verilog
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AnesBenmerzoug/Counter
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An N-bit counter module written in SystemC, VHDL and Verilog
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