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1. pulp_soc pulp_soc Public

   Forked from pulp-platform/pulp_soc

   pulp_soc is the core building component of PULP based SoCs

   SystemVerilog

2. dummy_vip dummy_vip Public

   Forked from pulp-soc-training/dummy_vip

   Files for the IP Integration Exercise

   SystemVerilog

3. axi axi Public

   Forked from pulp-platform/axi

   AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

   SystemVerilog

4. pulp_cluster pulp_cluster Public

   Forked from pulp-platform/pulp_cluster

   The multi-core cluster of a PULP system.

   SystemVerilog

5. regression_tests regression_tests Public

   Forked from pulp-platform/regression_tests

   C

6. iDMA iDMA Public

   Forked from pulp-platform/iDMA

   A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)

   SystemVerilog