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Support for attributes on port connections #30

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merged 10 commits into from
Jun 12, 2019

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mkurc-ant
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This PR adds support for defining attributes on port connections. Like that:

cell cell_instance (clk, rst, (* input_conn_attr = 10 *) inp, out);

I updated the RTLIL::SigSpec object so it holds a dict with attributes. Attributes are accepted by the Verilog and Ilang frontends. They are outputted by the Verilog, Ilang and JSON backends.

@mkurc-ant
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I already made some "performance" testing with and without this change. I ran Yosys with the 9-scalable-proc design with N=10. Each run was repeated 3 times to get rid of influence of random computer load.

YosysHQ/master:

CPU: user 6.94s system 0.05s, MEM: 221.55 MB total, 194.02 MB resident
Yosys 0.8+509 (git sha1 90ec2cda, gcc 7.4.0-1ubuntu1~18.04 -fPIC -Os)
Time spent: 21% 14x opt_merge (1 sec), 14% 7x techmap (1 sec), ...

CPU: user 6.97s system 0.04s, MEM: 221.55 MB total, 193.65 MB resident
Yosys 0.8+509 (git sha1 90ec2cda, gcc 7.4.0-1ubuntu1~18.04 -fPIC -Os)
Time spent: 21% 14x opt_merge (1 sec), 14% 7x techmap (1 sec), ...

CPU: user 6.92s system 0.07s, MEM: 221.55 MB total, 193.65 MB resident
Yosys 0.8+509 (git sha1 90ec2cda, gcc 7.4.0-1ubuntu1~18.04 -fPIC -Os)
Time spent: 21% 14x opt_merge (1 sec), 15% 7x techmap (1 sec), ...

This branch:

CPU: user 7.09s system 0.06s, MEM: 221.65 MB total, 193.83 MB resident
Yosys 0.8+498 (git sha1 1bdc7e9d, gcc 7.4.0-1ubuntu1~18.04 -fPIC -Os)
Time spent: 21% 14x opt_merge (1 sec), 15% 7x techmap (1 sec), ...

CPU: user 7.21s system 0.06s, MEM: 221.65 MB total, 194.07 MB resident
Yosys 0.8+498 (git sha1 1bdc7e9d, gcc 7.4.0-1ubuntu1~18.04 -fPIC -Os)
Time spent: 21% 14x opt_merge (1 sec), 14% 7x techmap (1 sec), ...

CPU: user 7.09s system 0.05s, MEM: 221.65 MB total, 194.14 MB resident
Yosys 0.8+498 (git sha1 1bdc7e9d, gcc 7.4.0-1ubuntu1~18.04 -fPIC -Os)
Time spent: 21% 14x opt_merge (1 sec), 15% 7x techmap (1 sec), ...

The memory usage is increased by ~100kB

@mkurc-ant mkurc-ant requested a review from mithro June 3, 2019 17:17
@mithro
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mithro commented Jun 4, 2019

LGTM but needs some tests to show it actually works?

@mkurc-ant
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Good, I'll work on adding those tests.

… tree.

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
…d from the AST

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
…rarily disabled due to lack support of certain features in Icarus Verilog which is used for testing

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
… pre-generated reference output. Failing tests not relevant to "attributes on port connections" functionality are temporarily disabled.

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
@mithro mithro merged commit 5f900f7 into SymbiFlow:master+wip Jun 12, 2019
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2 participants