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Support for attributes on port connections #30
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I already made some "performance" testing with and without this change. I ran Yosys with the YosysHQ/master:
This branch:
The memory usage is increased by ~100kB |
mithro
approved these changes
Jun 4, 2019
LGTM but needs some tests to show it actually works? |
Good, I'll work on adding those tests. |
… tree. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
…d from the AST Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
…rarily disabled due to lack support of certain features in Icarus Verilog which is used for testing Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
… pre-generated reference output. Failing tests not relevant to "attributes on port connections" functionality are temporarily disabled. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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mithro
approved these changes
Jun 12, 2019
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This PR adds support for defining attributes on port connections. Like that:
I updated the
RTLIL::SigSpec
object so it holds a dict with attributes. Attributes are accepted by the Verilog and Ilang frontends. They are outputted by the Verilog, Ilang and JSON backends.