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Merge pull request #30 from antmicro/attrs_on_port_conns
Support for attributes on port connections
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Original file line number | Diff line number | Diff line change |
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*.out* | ||
*.log |
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module bar(clk, rst, inp, out); | ||
input wire clk; | ||
input wire rst; | ||
input wire inp; | ||
output reg out; | ||
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always @(posedge clk) | ||
if (rst) out <= 1'd0; | ||
else out <= ~inp; | ||
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endmodule | ||
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module foo(clk, rst, inp, out); | ||
input wire clk; | ||
input wire rst; | ||
input wire inp; | ||
output wire out; | ||
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bar bar_instance (clk, rst, inp, out); | ||
endmodule | ||
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module bar(clk, rst, inp, out); | ||
(* this_is_clock = 1 *) | ||
input wire clk; | ||
(* this_is_reset = 1 *) | ||
input wire rst; | ||
input wire inp; | ||
(* an_output_register = 1*) | ||
output reg out; | ||
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always @(posedge clk) | ||
if (rst) out <= 1'd0; | ||
else out <= ~inp; | ||
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endmodule | ||
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module foo(clk, rst, inp, out); | ||
(* this_is_the_master_clock *) | ||
input wire clk; | ||
input wire rst; | ||
input wire inp; | ||
output wire out; | ||
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bar bar_instance (clk, rst, inp, out); | ||
endmodule | ||
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63 changes: 63 additions & 0 deletions
63
tests/reference-out/attrib02_port_decl/attrib02_port_decl.ref.il
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# Generated by Yosys 0.8+498 (git sha1 1bdc7e9d, gcc 7.4.0-1ubuntu1~18.04 -fPIC -Os) | ||
autoidx 3 | ||
attribute \cells_not_processed 1 | ||
attribute \src "attrib02_port_decl.v:1" | ||
module \bar | ||
attribute \src "attrib02_port_decl.v:10" | ||
wire $0\out[0:0] | ||
attribute \src "attrib02_port_decl.v:12" | ||
wire $not$attrib02_port_decl.v:12$2_Y | ||
attribute \src "attrib02_port_decl.v:3" | ||
attribute \this_is_clock 1 | ||
wire input 1 \clk | ||
attribute \src "attrib02_port_decl.v:6" | ||
wire input 3 \inp | ||
attribute \an_output_register 1 | ||
attribute \src "attrib02_port_decl.v:8" | ||
wire output 4 \out | ||
attribute \src "attrib02_port_decl.v:5" | ||
attribute \this_is_reset 1 | ||
wire input 2 \rst | ||
attribute \src "attrib02_port_decl.v:12" | ||
cell $not $not$attrib02_port_decl.v:12$2 | ||
parameter \A_SIGNED 0 | ||
parameter \A_WIDTH 1 | ||
parameter \Y_WIDTH 1 | ||
connect \A \inp | ||
connect \Y $not$attrib02_port_decl.v:12$2_Y | ||
end | ||
attribute \src "attrib02_port_decl.v:10" | ||
process $proc$attrib02_port_decl.v:10$1 | ||
assign $0\out[0:0] \out | ||
attribute \src "attrib02_port_decl.v:11" | ||
switch \rst | ||
case 1'1 | ||
assign $0\out[0:0] 1'0 | ||
case | ||
assign $0\out[0:0] $not$attrib02_port_decl.v:12$2_Y | ||
end | ||
sync posedge \clk | ||
update \out $0\out[0:0] | ||
end | ||
end | ||
attribute \cells_not_processed 1 | ||
attribute \src "attrib02_port_decl.v:16" | ||
module \foo | ||
attribute \src "attrib02_port_decl.v:18" | ||
attribute \this_is_the_master_clock 1 | ||
wire input 1 \clk | ||
attribute \src "attrib02_port_decl.v:20" | ||
wire input 3 \inp | ||
attribute \src "attrib02_port_decl.v:21" | ||
wire output 4 \out | ||
attribute \src "attrib02_port_decl.v:19" | ||
wire input 2 \rst | ||
attribute \module_not_derived 1 | ||
attribute \src "attrib02_port_decl.v:23" | ||
cell \bar \bar_instance | ||
connect $1 \clk | ||
connect $2 \rst | ||
connect $3 \inp | ||
connect $4 \out | ||
end | ||
end |
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