enable inference for RAMB36E1 #31

HackerFoo · 2019-06-05T19:16:26Z

No description provided.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

LUT6 is actually two LUT5s and a MUX. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

Working 7-series carry chains on VPR

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

Changes to support 7-series VPR flow

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

Correct map entries for some FF's

…f the "synth_xilinx" macro. Updated manual accordingly. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

…inx" flow accordingly. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Update yosys with setundef

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Merge WREDUCE fix to Symbiflow branch

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

…backend Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

…erilog frontend/backend Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

…e JSON backend Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Support for attributes on parameters in Verilog

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

Previous logic was using CO[Y_WIDTH], which is downstream of another MUXCY. Rather than using CO[Y_WIDTH], O[Y_WIDTH] with S[Y_WIDTH] = 0 works just as well. For reference: O[N] = CO[N-1] ^ S[N] So if S[N] = 0, O[N] === CO[N-1], which is the desired state. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

Update CARRY4 sim model to handle disconnected CIN signal.

Dedicated top of carry pin is sourced from O[Y_WIDTH].

litghost · 2019-06-05T20:56:15Z

techlibs/xilinx/brams.txt

-#  or_next_if_better
-#endmatch
+match $__XILINX_RAMB36_TDP
+  min bits 4096


Should RAMB36 and RAMB18 have the same min bits?

I'm not sure how this value is calculated. Why shouldn't there be less than 4k bits used, if it is otherwise the best match?

It would be nice to assign a weight or polynomial, or some soft limit, rather than just hard limits.

I guess that is what "efficiency" is for?

Yeah, but it's just the percentage of used bits. For example, may some types of memory use less power or have less delay, or maybe it's better to fill one RAM 90% than use two at 95% efficiency, or one at 100% and one at 50% for a greedy algorithm. I guess you can prioritize them by changing the order, but then they would have to have the same exact efficiency for it to matter.

Anyway, I don't know where the 4k bit minimum comes from, so I didn't modify it.

Another thing, the 8/16/32 bit modes are weird in that you can waste e.g. 1/9th of the memory and yet have an efficiency of 100% because it's 100% of the available capacity in that mode.

Another thing, the 8/16/32 bit modes are weird in that you can waste e.g. 1/9th of the memory and yet have an efficiency of 100% because it's 100% of the available capacity in that mode.

A narrower mode is deeper, so efficiency is non-linear.

Signed-off-by: Dusty DeWeese <dustin.deweese@gmail.com>

HackerFoo · 2019-06-06T18:14:16Z

I'm going to put off adding support for 8/16/32-bit widths for later, since it's not trivial and not needed right now.

@litghost What value do you suggest for min bits?

litghost · 2019-06-06T18:14:52Z

@litghost What value do you suggest for min bits?

Let's leave it alone.

litghost · 2019-06-06T19:05:39Z

Have you tested the relevant circuits in symbiflow? E.g. murax, picosoc and scalable proc? Which of these now instance the larger primitive?

litghost · 2019-06-12T17:54:06Z

@HackerFoo Please report hardware testing status for:

Scalable proc
Murax
Picosoc

HackerFoo · 2019-06-12T17:59:23Z

I haven't tried scalable proc yet
Murax works, but doesn't use 36k blocks
PicoSoC does use them, but doesn't work with or without them, so I need to find a working configuration.

HackerFoo · 2019-06-12T18:34:09Z

top_bram_n3 also doesn't work without 36k RAM inference.

rx:'054BB395' pat:'054BB395' V
rx:'06D2F54C' pat:'06D2F54C' V
Got 5 consecutive matches. In sync.
MISMATCH! (rx='4C736D44', pat='A3C391EB'), Sync lost!
rx:'A3C391EB' pat:'A3C391EB' V
rx:'0150BAB0' pat:'0150BAB0' V
rx:'0060ED28' pat:'0060ED28' V
rx:'054BB395' pat:'054BB395' V
rx:'06D2F54C' pat:'06D2F54C' V
Got 5 consecutive matches. In sync.
MISMATCH! (rx='4C736D44', pat='A3C391EB'), Sync lost!
rx:'A3C391EB' pat:'A3C391EB' V
rx:'0150BAB0' pat:'0150BAB0' V

litghost · 2019-06-12T18:35:04Z

top_bram_n3 also doesn't work without 36k RAM inference.

Does top_bram_n1?

HackerFoo · 2019-06-12T18:44:13Z

top_bram_n1 fails too.

litghost and others added 30 commits October 23, 2018 13:12

xilinx: Add explicit carry techmap for vpr.

9eadccb

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

techlibs/xilinx: LUT6 doesn't exist.

c75770f

LUT6 is actually two LUT5s and a MUX. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

Working artix7 carry chains on VPR.

37d36af

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

Adding WIP note.

e7cfd68

Fix formatting.

67fd1fa

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

Merge pull request #2 from litghost/xilinx-vpr-carry-chains

1d62203

Working 7-series carry chains on VPR

Update DRAM models.

5fa9556

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

Carry fixes.

088e8c8

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

Add support for various DRAM modes.

3e1dd58

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

Rename techmap to ensure order in eblif so that VPR packer works nicely.

4596bf5

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

Most DRAM modes working.

9f0cd50

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

Fix assorted errors.

9332eca

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

Working sim and add stubs for DRAMs.

3400c52

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

Add FF INIT.

2dc44dc

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

Use explicit initial statements for RAMs.

a3e64fd

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

Remove dead-end models.

c6f41dd

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

Merge pull request #5 from litghost/vpr-dram

f340adf

Changes to support 7-series VPR flow

Correct map entries for some FF's

c834dee

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

Merge pull request #6 from litghost/correct_map

b6119fa

Correct map entries for some FF's

Added correct techmap for Xilinx 7-series primitives. Modified flow o…

f48c450

…f the "synth_xilinx" macro. Updated manual accordingly. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Refactored techmap definition for Vivado and VPR. Modified "synth_xil…

6a5f5ad

…inx" flow accordingly. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Updated help text in synth_xilinx.cc

c70c1e0

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Updated reference manual

9855a09

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Replaced 4 spaces to tabs.

de7c405

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Unified LUT flow for Vivado and VPR

ea9d46c

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Merge branch 'master' into master+wip

4a4dc76

Merge pull request #9 from litghost/update_yosys_with_setundef

79eca4e

Update yosys with setundef

Added negedge sensitive FFs recognized by Vivado, also to the VPR flow.

5eacb96

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Merge branch 'fix_reduce_on_ff' into master+wip

cf1a2c6

Merge pull request #10 from litghost/master+wip

ec7f99f

Merge WREDUCE fix to Symbiflow branch

mkurc-ant and others added 13 commits May 22, 2019 12:03

Added retrieving parameter information to Python wrapper

0a71def

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Added escaping of module parameters starting with "$" to the verilog …

73e589e

…backend Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Added round-trip tests for Verilog and Ilang frontend/backend

b2c430a

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Added support for default value of floating point parameters to the V…

a05a44c

…erilog frontend/backend Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Added outputting of floating point default values of parameters to th…

156580e

…e JSON backend Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Added round-trip test for various Verilog parameter types

326ea4a

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Merge pull request #25 from antmicro/parameter_support

a69222f

Support for attributes on parameters in Verilog

Merge remote-tracking branch 'upstream/master' into master+wip

fa181bd

Update CARRY4 sim model to handle disconnected CIN signal.

fc25a09

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

Add arith techmap sanity testbench's.

f3f0943

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

Merge pull request #28 from litghost/correct_cin_model

b10f244

Update CARRY4 sim model to handle disconnected CIN signal.

Merge pull request #29 from litghost/fix_carry_techmap

8d943b4

Dedicated top of carry pin is sourced from O[Y_WIDTH].

HackerFoo requested a review from litghost June 5, 2019 19:16

litghost requested changes Jun 5, 2019

View reviewed changes

enable inference for RAMB36E1

13af585

Signed-off-by: Dusty DeWeese <dustin.deweese@gmail.com>

HackerFoo marked this pull request as ready for review June 6, 2019 18:12

litghost mentioned this pull request Jun 12, 2019

Ensure that important RAM modes are exposed to Yosys #35

Open

2 tasks

litghost added this to To do in XC7 Timing burn down Jun 12, 2019

litghost force-pushed the master+wip branch from 5f900f7 to 5a73f39 Compare August 19, 2019 16:00

litghost mentioned this pull request Jan 23, 2020

32-bit LUT-RAM are not correctly implemented f4pga/f4pga-arch-defs#1269

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HackerFoo closed this May 19, 2020

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enable inference for RAMB36E1 #31

enable inference for RAMB36E1 #31

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enable inference for RAMB36E1 #31

enable inference for RAMB36E1 #31

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