Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Add support for QuickLogic devices #89

Open
wants to merge 76 commits into
base: master
Choose a base branch
from

Conversation

rw1nkler
Copy link

This PR adds support for the following QuickLogic devices:

glatosinski and others added 30 commits October 12, 2020 13:25
Fixed syntax error and set the WIDTH of signed_mult to 32 for default. (Maciej Kurc<mkurc@antmicro.com>)
QL: cells_sim: fix port definitions for buffers (Karol Gugala<kgugala@antmicro.com>)
QL: cells_map: map Valid_mult for mult16x16 (Karol Gugala<kgugala@antmicro.com>)
QL: cells_sim: update simulation models (Karol Gugala<kgugala@antmicro.com>)
QL: cells_sim: fix dff in logic_cell_macro (Karol Gugala<kgugala@antmicro.com>)
QL: cells_sim: remove commented out code (Karol Gugala<kgugala@antmicro.com>)
QL: use (* iopad_external_pin *) (Karol Gugala<kgugala@antmicro.com>)
QL: synth: do not check for empty top_opt (Karol Gugala<kgugala@antmicro.com>)
QL: replace YS_OVERRIDE -> override (Karol Gugala<kgugala@antmicro.com>)
Fixed incorrect techmap for mux4x0 (Maciej Kurc<mkurc@antmicro.com>)
QuickLogic: flatten designs by default (Karol Gugala<kgugala@antmicro.com>)
QuickLogic: add autoname (Karol Gugala<kgugala@antmicro.com>)
QuickLogic: add CODEOWNERS entry (Karol Gugala<kgugala@antmicro.com>)
QuickLogic: refactor synth_quicklogic (Karol Gugala<kgugala@antmicro.com>)
QuickLogic: Add MUX4 and MUX8 mappings (Karol Gugala<kgugala@antmicro.com>)
QL: Updated the flow of synth_quicklogic (Maciej Kurc<mkurc@antmicro.com>)
QL: Added more test cases (Maciej Kurc<mkurc@antmicro.com>)
Fixed a typo (Maciej Kurc<mkurc@antmicro.com>)
Added labels to the synth_quicklogic flow (Maciej Kurc<mkurc@antmicro.com>)
Fixed an undeclared signal bug and FF models in quicklogic/cells_sim.v (Maciej Kurc<mkurc@antmicro.com>)
quicklogic: add gpio_cell_macro sim model (Karol Gugala<kgugala@antmicro.com>)
Updated flip-flop implementations (Grzegorz Latosinski<glatosinski@antmicro.com>)
Changed the Quicklogic synth flow to use clkbufmap. Updated cells_sim.v and tests. (Maciej Kurc<mkurc@antmicro.com>)
Removed techmaps for gate-level builtin cells. (Maciej Kurc<mkurc@antmicro.com>)
Added tests for synth_quicklogic. (Maciej Kurc<mkurc@antmicro.com>)
QL: add gpio_macro_cell definition (Karol Gugala<kgugala@antmicro.com>)
Fixed logic_cell_macro model in cells_sim.v (Maciej Kurc<mkurc@antmicro.com>)
quicklogic: Added command for assigning undriven ports (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Removed synthesis comments (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Added implementation of the logic cell (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Used help_mode to alter the run calls (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Moved peepopt before techmap (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Removed excessive proc calls (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Removed -exe flag (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Added qlal4s3_mult_cell_macro (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Fixed indents for qlal4s3b_cell_macro (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Added logic_cell_macro (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: fix segfault in help synth_quicklogic (Karol Gugala<kgugala@antmicro.com>)
quicklogic: remove redundant bipad module (Karol Gugala<kgugala@antmicro.com>)
quicklogic: Added support for bipad (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Added support for latches (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Added dffsc module (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Add IO pads only to the top module IO ports (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Improved cleaning routines (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Added mapping from 32x32 multiplier to 16x16 multiplier (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Fixed '-top' flag handling for synth_quicklogic (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Fixed call to hierarchy check (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Added keep directive for Quicklogic CPU blackbox (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Renamed multiply blocks to convention accepted by SpDE (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Updated cells_sim.v and cells_map.v (Maciej Kurc<mkurc@antmicro.com>)
quicklogic: Corrected simulation models of LUTs for Quicklogic. (Maciej Kurc<mkurc@antmicro.com>)
quicklogic: Added mapping of VCC and GND in design to logic_1 and logic_0 (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Introduced VCC (logic_1) and GND (logic_0) blocks (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: added minor blocks (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: added multiplier blocks (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: added RAM block (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Added black boxes for hard CPU and gclkbuff (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Fixed mapping for QuickLogic LUTs (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Specialized all inpads assigned to asynchronous inputs to ckpads. (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Fixed the output name for ckpad. (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Fixed missing registered FF outputs. (Maciej Kurc<mkurc@antmicro.com>)
quicklogic: Added splitting the ports (SpDE support) (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Added support for IO pads and CLK pads (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Added address inversion for QuickLogic LUTs (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Removed VCC/GND entries (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Added IO pads to the QuickLogic script (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Fixed cells mapping for inverted signals (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Updated the library of available cells for QuickLogic (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: synth_quicklogic: Added loading cells library for QuickLogic (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Created an initial script for MUX-based FPGAs (Grzegorz Latosinski<glatosinski@antmicro.com>)

Signed-off-by: Grzegorz Latosinski <glatosinski@antmicro.com>
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Signed-off-by: Karol Gugala <kgugala@antmicro.com>

Co-authored-by: Grzegorz Latosinski <glatosinski@antmicro.com>
Co-authored-by: Maciej Kurc <mkurc@antmicro.com>
Co-authored-by: Karol Gugala <kgugala@antmicro.com>
Makefile.inc - added Mult, RAM and FIFO Macro details
cells_sim.v - removed inpadff, outpadff, bipadiff, bipadoff and bipadioff definitions

Signed-off-by: Rakesh Moolacheri <rakeshm@quicklogic.com>
Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
QL: AP: tweak LUT costs to prefer bigger LUTs (Karol Gugala<kgugala@antmicro.com>)
QL: techmaps: split LUT techmaps for PP3 and AP3 (Karol Gugala<kgugala@antmicro.com>)
QL: AP3: set lut costs so LU4 is preferred one (Karol Gugala<kgugala@antmicro.com>)
QL: AP3: fix sim and map Verilogs (Karol Gugala<kgugala@antmicro.com>)

Signed-off-by: Karol Gugala <kgugala@antmicro.com>
Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
Signed-off-by: kkumar23 <61860672+kkumar23@users.noreply.github.com>
Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
… one cell as add

Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
Lalit Sharma and others added 21 commits October 12, 2020 13:26
Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
…_reg in AP2

Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Before this change, yosys required 4096 bits (or at least 50%)
of the bits in a RAM to be used, in order to implement it as a
PB-RAM. Since there are less than 1000 FFs available in the FPGA
it means that any memory using somewhere between 1k and 4k bits
will not fit in the device.

This lowers the requirements on RAM efficiency to be more in line
with the iCE40 backend, which uses comparably sized FPGAs

Signed-off-by: Olof Kindgren <olof.kindgren@gmail.com>
Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
Copy link

@litghost litghost left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

There are couple open questions here:

  • Does this belong in the downstream fork at all?
  • If it does belong down here, it oaught to be in wip/ branch, rather than merged directly onto the downstream master branch

@mithro What's the plan here?

@rw1nkler
Copy link
Author

rw1nkler commented Oct 12, 2020

This PR has been created to discuss the changes and then add it as a wip/ branch to SymbiFlow Yosys.
The code comes from the QuickLogic Yosys fork (which is actively developed):
https://github.com/QuickLogic-Corp/yosys/tree/quicklogic-rebased

GitHub
Yosys Open SYnthesis Suite. Contribute to QuickLogic-Corp/yosys development by creating an account on GitHub.

@rw1nkler
Copy link
Author

rw1nkler commented Nov 2, 2020

Is there any other issue that needs to be addressed before creating wip/quicklogic branch and regenerating Yosys master+wip branch?

@litghost
Copy link

litghost commented Nov 2, 2020

Is there any other issue that needs to be addressed before creating wip/quicklogic branch and regenerating Yosys master+wip branch?

I think the broader issue is how to maintain long term maintenance of this wip/ branch. One of the recent pushes has been to eliminate wip/ branches, either by getting the patches merged upstream, or in the case of yosys, making plugins rather than modifying yosys directly. Ideally this would go into upstream yosys, but I understand that might be hard to impossible.

If getting into upstream yosys is not going to happen, then I believe converting this PR into a plugin, likely under its own project, is my preferred path forward.

@rw1nkler
Copy link
Author

rw1nkler commented Nov 6, 2020

I believe converting this PR into a plugin, likely under its own project, is my preferred path forward.

Ok, I will create a PR which will add those changes as a separate Yosys plugin.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

None yet

9 participants