Add support for QuickLogic devices

CODEOWNERS

@@ -26,6 +26,7 @@ passes/opt/opt_lut.cc          @whitequark
 # accidentally disable any of the above rules.
 
 techlibs/intel_alm/            @ZirconiumX
+techlibs/quicklogic/           @kgugala
 
 # pyosys
 misc/*.py                      @btut

passes/pmgen/Makefile.inc

@@ -46,3 +46,9 @@ passes/pmgen/peepopt_pm.h: passes/pmgen/pmgen.py $(PEEPOPT_PATTERN)
 OBJS += passes/pmgen/xilinx_srl.o
 passes/pmgen/xilinx_srl.o: passes/pmgen/xilinx_srl_pm.h
 $(eval $(call add_extra_objs,passes/pmgen/xilinx_srl_pm.h))
+
+# --------------------------------------
+
+OBJS += passes/pmgen/ap3_wrapcarry.o
+passes/pmgen/ap3_wrapcarry.o: passes/pmgen/ap3_wrapcarry_pm.h
+$(eval $(call add_extra_objs,passes/pmgen/ap3_wrapcarry_pm.h))

passes/pmgen/ap3_wrapcarry.cc

@@ -0,0 +1,158 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2020 QuickLogic Corp.
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+#include "passes/pmgen/ap3_wrapcarry_pm.h"
+
+void create_ap3_wrapcarry(ap3_wrapcarry_pm &pm)
+{
+	auto &st = pm.st_ap3_wrapcarry;
+
+#if 0
+	log("\n");
+	log("carry: %s\n", log_id(st.carry, "--"));
+	log("lut:   %s\n", log_id(st.lut, "--"));
+#endif
+
+	log("  replacing LUT4 + QL_CARRY with $__AP3_CARRY_WRAPPER cell.\n");
+
+	Cell *cell = pm.module->addCell(NEW_ID, ID($__AP3_CARRY_WRAPPER));
+	pm.module->swap_names(cell, st.carry);
+
+	cell->setPort(ID::A, st.carry->getPort(ID(I0)));
+	cell->setPort(ID::B, st.carry->getPort(ID(I1)));
+	auto CI = st.carry->getPort(ID::CI);
+	cell->setPort(ID::CI, CI);
+	cell->setPort(ID::CO, st.carry->getPort(ID::CO));
+
+	auto I2 = st.lut->getPort(ID(I2));
+	if (pm.sigmap(CI) == pm.sigmap(I2)) {
+		cell->setParam(ID(I2_IS_CI), State::S1);
+		I2 = State::Sx;
+	}
+	else
+		cell->setParam(ID(I2_IS_CI), State::S0);
+	cell->setPort(ID(I2), I2);
+	cell->setPort(ID(I3), st.lut->getPort(ID(I3)));
+	cell->setPort(ID::O, st.lut->getPort(ID::O));
+	cell->setParam(ID::LUT, st.lut->getParam(ID(INIT)));
+
+	for (const auto &a : st.carry->attributes)
+		cell->attributes[stringf("\\QL_CARRY.%s", a.first.c_str())] = a.second;
+	for (const auto &a : st.lut->attributes)
+		cell->attributes[stringf("\\LUT4.%s", a.first.c_str())] = a.second;
+	cell->attributes[ID(LUT4.name)] = Const(st.lut->name.str());
+	if (st.carry->get_bool_attribute(ID::keep) || st.lut->get_bool_attribute(ID::keep))
+		cell->attributes[ID::keep] = true;
+
+	pm.autoremove(st.carry);
+	pm.autoremove(st.lut);
+}
+
+struct AP3WrapCarryPass : public Pass {
+	AP3WrapCarryPass() : Pass("ap3_wrapcarry", "AP3: wrap carries") { }
+	void help() override
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    ap3_wrapcarry [selection]\n");
+		log("\n");
+		log("Wrap manually instantiated QL_CARRY cells, along with their associated LUT4s,\n");
+		log("into an internal $__AP3_CARRY_WRAPPER cell for preservation across technology\n");
+		log("mapping.\n");
+		log("\n");
+		log("Attributes on both cells will have their names prefixed with 'QL_CARRY.' or\n");
+		log("'LUT4.' and attached to the wrapping cell.\n");
+		log("A (* keep *) attribute on either cell will be logically OR-ed together.\n");
+		log("\n");
+		log("    -unwrap\n");
+		log("        unwrap $__AP3_CARRY_WRAPPER cells back into QL_CARRYs and LUT4s,\n");
+		log("        including restoring their attributes.\n");
+		log("\n");
+	}
+	void execute(std::vector<std::string> args, RTLIL::Design *design) override
+	{
+		bool unwrap = false;
+
+		log_header(design, "Executing ap3_wrapcarry pass (wrap carries).\n");
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++)
+		{
+			if (args[argidx] == "-unwrap") {
+				unwrap = true;
+				continue;
+			}
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		for (auto module : design->selected_modules()) {
+			if (!unwrap) {
+				ap3_wrapcarry_pm(module, module->selected_cells()).run_ap3_wrapcarry(create_ap3_wrapcarry);
+			} else {
+				for (auto cell : module->selected_cells()) {
+					if (cell->type != ID($__AP3_CARRY_WRAPPER))
+						continue;
+
+					auto carry = module->addCell(NEW_ID, ID(QL_CARRY));
+					carry->setPort(ID(I0), cell->getPort(ID::A));
+					carry->setPort(ID(I1), cell->getPort(ID::B));
+					carry->setPort(ID::CI, cell->getPort(ID::CI));
+					carry->setPort(ID::CO, cell->getPort(ID::CO));
+					module->swap_names(carry, cell);
+					auto lut_name = cell->attributes.at(ID(LUT4.name), Const(NEW_ID.str())).decode_string();
+					auto lut = module->addCell(lut_name, ID($lut));
+					lut->setParam(ID::WIDTH, 4);
+					lut->setParam(ID::LUT, cell->getParam(ID::LUT));
+					auto I2 = cell->getPort(cell->getParam(ID(I2_IS_CI)).as_bool() ? ID::CI : ID(I2));
+					lut->setPort(ID::A, {cell->getPort(ID(I3)), I2, cell->getPort(ID::B), cell->getPort(ID::A)});
+					lut->setPort(ID::Y, cell->getPort(ID::O));
+
+					Const src;
+					for (const auto &a : cell->attributes)
+						if (a.first.begins_with("\\QL_CARRY.\\"))
+							carry->attributes[a.first.c_str() + strlen("\\QL_CARRY.")] = a.second;
+						else if (a.first.begins_with("\\LUT4.\\"))
+							lut->attributes[a.first.c_str() + strlen("\\LUT4.")] = a.second;
+						else if (a.first == ID::src)
+							src = a.second;
+						else if (a.first.in(ID(LUT4.name), ID::keep, ID::module_not_derived))
+							continue;
+						else
+							log_abort();
+
+					if (!src.empty()) {
+						carry->attributes.insert(std::make_pair(ID::src, src));
+						lut->attributes.insert(std::make_pair(ID::src, src));
+					}
+
+					module->remove(cell);
+				}
+			}
+		}
+	}
+} AP3WrapCarryPass;
+
+PRIVATE_NAMESPACE_END

passes/pmgen/ap3_wrapcarry.pmg

@@ -0,0 +1,15 @@
+pattern ap3_wrapcarry
+
+match carry
+	select carry->type.in(\QL_CARRY)
+endmatch
+
+match lut
+	select lut->type.in(\LUT4)
+	index <SigSpec> port(lut, \I0) === port(carry, \I0)
+	index <SigSpec> port(lut, \I1) === port(carry, \I1)
+endmatch
+
+code
+	accept;
+endcode

techlibs/quicklogic/MULT_16BIT_X2.v

@@ -0,0 +1,34 @@
+module MULT_16BIT_X2 ( Amult1, Bmult1, Valid_mult1, Cmult1,
+                       Amult2, Bmult2, Valid_mult2, Cmult2
+                     );
+
+input [15:0] Amult1;
+input [15:0] Bmult1;
+input Valid_mult1;
+output [31:0] Cmult1;
+
+input [15:0] Amult2;
+input [15:0] Bmult2;
+input Valid_mult2;
+output [31:0] Cmult2;
+
+wire [31:0] amult_int;
+wire [31:0] bmult_int;
+wire [63:0] cmult_int;
+wire [1:0] valit_int;
+
+assign valit_int = {Valid_mult2,Valid_mult1};
+assign amult_int = {Amult2,Amult1};
+assign bmult_int = {Bmult2,Bmult1};
+assign Cmult1 = cmult_int[31:0];
+assign Cmult2 = cmult_int[63:32];
+
+//qlal4s3_mult_cell_macro
+qlal4s3_mult_cell_macro u_qlal4s3_mult_cell_macro (
+    .Amult(amult_int),
+    .Bmult(bmult_int),
+    .Valid_mult(valit_int),
+    .sel_mul_32x32(1'b0),
+    .Cmult(cmult_int)
+);
+endmodule

techlibs/quicklogic/MULT_32BIT.v

@@ -0,0 +1,21 @@
+module MULT_32BIT (Amult, Bmult, Valid_mult, Cmult);
+
+input [31:0] Amult;
+input [31:0] Bmult;
+input  Valid_mult;
+output [63:0] Cmult;
+
+wire [1:0] valit_int;
+
+assign valit_int = {Valid_mult,Valid_mult};
+
+//qlal4s3_mult_cell_macro
+qlal4s3_mult_cell_macro u_qlal4s3_mult_cell_macro (
+    .Amult(Amult),
+    .Bmult(Bmult),
+    .Valid_mult(valit_int),
+    .sel_mul_32x32(1'b1),
+    .Cmult(Cmult)
+);
+
+endmodule

techlibs/quicklogic/Makefile.inc

@@ -0,0 +1,53 @@
+OBJS += techlibs/quicklogic/synth_quicklogic.o
+#OBJS += techlibs/quicklogic/ap3_opt.o
+OBJS += techlibs/quicklogic/quicklogic_eqn.o
+OBJS += techlibs/quicklogic/pp3_braminit.o
+#OBJS += techlibs/quicklogic/quicklogic_fixcarry.o
+
+
+$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/ap3_ffs_map.v))
+$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/ap2_ffs_map.v))
+$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/pp3_ffs_map.v))
+$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/ap3_lut_map.v))
+$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/ap2_lut_map.v))
+$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/pp3_lut_map.v))
+$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/ap3_latches_map.v))
+$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/ap2_latches_map.v))
+$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/pp3_latches_map.v))
+$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/ap3_cells_map.v))
+$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/ap2_cells_map.v))
+$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/pp3_cells_map.v))
+$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/ap3_arith_map.v))
+$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/ap2_arith_map.v))
+$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/ap2_io_map.v))
+$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/ap3_io_map.v))
+$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/cells_sim.v))
+$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/pp3_cells_sim.v))
+
+$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/ap3_cells_sim.v))
+$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/ap2_cells_sim.v))
+
+$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/MULT_16BIT_X2.v))
+$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/MULT_32BIT.v))
+$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/abc9_model.v))
+$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/pp3_brams.txt))
+$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/pp3_brams_map.v))
+
+$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/pp3_lutdefs.txt))
+$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/ap2_lutdefs.txt))
+$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/ap3_lutdefs.txt))
+
+EXTRA_OBJS += techlibs/quicklogic/brams_init.mk 
+.SECONDARY: techlibs/quicklogic/brams_init.mk 
+
+techlibs/quicklogic/brams_init.mk: techlibs/quicklogic/brams_init.py
+	$(Q) mkdir -p techlibs/quicklogic
+	$(P) $(PYTHON_EXECUTABLE) $<
+	$(Q) touch $@
+
+
+techlibs/quicklogic/bram_init_8_16.vh: techlibs/quicklogic/brams_init.mk
+techlibs/quicklogic/bram_init_32.vh: techlibs/quicklogic/brams_init.mk
+
+$(eval $(call add_gen_share_file,share/quicklogic,techlibs/quicklogic/bram_init_8_16.vh))
+$(eval $(call add_gen_share_file,share/quicklogic,techlibs/quicklogic/bram_init_32.vh))

techlibs/quicklogic/abc9_model.v

@@ -0,0 +1,29 @@
+(* abc9_box, lib_whitebox *)
+module \$__AP3_CARRY_WRAPPER (
+	(* abc9_carry *)
+	output CO,
+	output O,
+	input A, B,
+	(* abc9_carry *)
+	input CI,
+	input I2, I3
+);
+	parameter LUT = 0;
+	parameter I2_IS_CI = 0;
+	wire I2_OR_CI = I2_IS_CI ? CI : I2;
+	QL_CARRY carry (
+		.I0(A),
+		.I1(B),
+		.CI(CI),
+		.CO(CO)
+	);
+	LUT4 #(
+		.INIT(LUT)
+	) adder (
+		.I0(A),
+		.I1(B),
+		.I2(I2_OR_CI),
+		.I3(I3),
+		.O(O)
+	);
+endmodule

techlibs/quicklogic/ap2_arith_map.v

@@ -0,0 +1,64 @@
+(* techmap_celltype = "$alu" *)
+module _80_quicklogic_alu (A, B, CI, BI, X, Y, CO);
+    parameter A_SIGNED = 0;
+    parameter B_SIGNED = 0;
+    parameter A_WIDTH  = 1;
+    parameter B_WIDTH  = 1;
+    parameter Y_WIDTH  = 1;
+
+    (* force_downto *)
+    input [A_WIDTH-1:0] A;
+    (* force_downto *)
+    input [B_WIDTH-1:0] B;
+    (* force_downto *)
+    output [Y_WIDTH-1:0] X, Y;
+
+    input CI, BI;
+    (* force_downto *)
+    output [Y_WIDTH-1:0] CO;
+
+    wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
+
+    (* force_downto *)
+    wire [Y_WIDTH-1:0] A_buf, B_buf;
+    \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
+    \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+
+    (* force_downto *)
+    wire [Y_WIDTH-1:0] AA = A_buf;
+    (* force_downto *)
+    wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
+    //(* force_downto *)
+    //wire [Y_WIDTH-1:0] C = {CO, CI};
+
+    full_adder first_inst(
+            .A(AA[0]),
+            .B(BB[0]),
+			.CI(CI),
+			.CO(CO[0]),
+			.S(Y[0]));
+
+    genvar i;
+    generate for (i = 1; i < Y_WIDTH-1; i = i + 1) begin: slice
+        full_adder inst_i (
+			.A(AA[i]),
+			.B(BB[i]),
+			.CI(CO[i-1]),
+			.CO(CO[i]),
+			.S(Y[i])
+		);
+
+    end: slice	  
+    endgenerate
+
+    full_adder inst_last (
+        .A(AA[Y_WIDTH-1]),
+        .B(BB[Y_WIDTH-1]),
+        .CI(CO[Y_WIDTH-2]),
+        .CO(CO[Y_WIDTH-1]),
+        .S(Y[Y_WIDTH-1])
+    );
+
+    /* End implementation */
+    assign X = AA ^ BB;
+endmodule