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Add support for QuickLogic devices #89

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Add support for QuickLogic devices #89

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Commits on Oct 12, 2020

  1. Initial synth_quicklogic implementation 

    Fixed syntax error and set the WIDTH of signed_mult to 32 for default. (Maciej Kurc<mkurc@antmicro.com>)
QL: cells_sim: fix port definitions for buffers (Karol Gugala<kgugala@antmicro.com>)
QL: cells_map: map Valid_mult for mult16x16 (Karol Gugala<kgugala@antmicro.com>)
QL: cells_sim: update simulation models (Karol Gugala<kgugala@antmicro.com>)
QL: cells_sim: fix dff in logic_cell_macro (Karol Gugala<kgugala@antmicro.com>)
QL: cells_sim: remove commented out code (Karol Gugala<kgugala@antmicro.com>)
QL: use (* iopad_external_pin *) (Karol Gugala<kgugala@antmicro.com>)
QL: synth: do not check for empty top_opt (Karol Gugala<kgugala@antmicro.com>)
QL: replace YS_OVERRIDE -> override (Karol Gugala<kgugala@antmicro.com>)
Fixed incorrect techmap for mux4x0 (Maciej Kurc<mkurc@antmicro.com>)
QuickLogic: flatten designs by default (Karol Gugala<kgugala@antmicro.com>)
QuickLogic: add autoname (Karol Gugala<kgugala@antmicro.com>)
QuickLogic: add CODEOWNERS entry (Karol Gugala<kgugala@antmicro.com>)
QuickLogic: refactor synth_quicklogic (Karol Gugala<kgugala@antmicro.com>)
QuickLogic: Add MUX4 and MUX8 mappings (Karol Gugala<kgugala@antmicro.com>)
QL: Updated the flow of synth_quicklogic (Maciej Kurc<mkurc@antmicro.com>)
QL: Added more test cases (Maciej Kurc<mkurc@antmicro.com>)
Fixed a typo (Maciej Kurc<mkurc@antmicro.com>)
Added labels to the synth_quicklogic flow (Maciej Kurc<mkurc@antmicro.com>)
Fixed an undeclared signal bug and FF models in quicklogic/cells_sim.v (Maciej Kurc<mkurc@antmicro.com>)
quicklogic: add gpio_cell_macro sim model (Karol Gugala<kgugala@antmicro.com>)
Updated flip-flop implementations (Grzegorz Latosinski<glatosinski@antmicro.com>)
Changed the Quicklogic synth flow to use clkbufmap. Updated cells_sim.v and tests. (Maciej Kurc<mkurc@antmicro.com>)
Removed techmaps for gate-level builtin cells. (Maciej Kurc<mkurc@antmicro.com>)
Added tests for synth_quicklogic. (Maciej Kurc<mkurc@antmicro.com>)
QL: add gpio_macro_cell definition (Karol Gugala<kgugala@antmicro.com>)
Fixed logic_cell_macro model in cells_sim.v (Maciej Kurc<mkurc@antmicro.com>)
quicklogic: Added command for assigning undriven ports (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Removed synthesis comments (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Added implementation of the logic cell (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Used help_mode to alter the run calls (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Moved peepopt before techmap (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Removed excessive proc calls (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Removed -exe flag (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Added qlal4s3_mult_cell_macro (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Fixed indents for qlal4s3b_cell_macro (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Added logic_cell_macro (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: fix segfault in help synth_quicklogic (Karol Gugala<kgugala@antmicro.com>)
quicklogic: remove redundant bipad module (Karol Gugala<kgugala@antmicro.com>)
quicklogic: Added support for bipad (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Added support for latches (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Added dffsc module (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Add IO pads only to the top module IO ports (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Improved cleaning routines (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Added mapping from 32x32 multiplier to 16x16 multiplier (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Fixed '-top' flag handling for synth_quicklogic (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Fixed call to hierarchy check (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Added keep directive for Quicklogic CPU blackbox (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Renamed multiply blocks to convention accepted by SpDE (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Updated cells_sim.v and cells_map.v (Maciej Kurc<mkurc@antmicro.com>)
quicklogic: Corrected simulation models of LUTs for Quicklogic. (Maciej Kurc<mkurc@antmicro.com>)
quicklogic: Added mapping of VCC and GND in design to logic_1 and logic_0 (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Introduced VCC (logic_1) and GND (logic_0) blocks (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: added minor blocks (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: added multiplier blocks (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: added RAM block (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Added black boxes for hard CPU and gclkbuff (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Fixed mapping for QuickLogic LUTs (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Specialized all inpads assigned to asynchronous inputs to ckpads. (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Fixed the output name for ckpad. (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Fixed missing registered FF outputs. (Maciej Kurc<mkurc@antmicro.com>)
quicklogic: Added splitting the ports (SpDE support) (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Added support for IO pads and CLK pads (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Added address inversion for QuickLogic LUTs (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Removed VCC/GND entries (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Added IO pads to the QuickLogic script (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Fixed cells mapping for inverted signals (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Updated the library of available cells for QuickLogic (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: synth_quicklogic: Added loading cells library for QuickLogic (Grzegorz Latosinski<glatosinski@antmicro.com>)
quicklogic: Created an initial script for MUX-based FPGAs (Grzegorz Latosinski<glatosinski@antmicro.com>)

Signed-off-by: Grzegorz Latosinski <glatosinski@antmicro.com>
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Signed-off-by: Karol Gugala <kgugala@antmicro.com>

Co-authored-by: Grzegorz Latosinski <glatosinski@antmicro.com>
Co-authored-by: Maciej Kurc <mkurc@antmicro.com>
Co-authored-by: Karol Gugala <kgugala@antmicro.com>
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  2. added ram, fifo and multiplier macros 

    Makefile.inc - added Mult, RAM and FIFO Macro details
cells_sim.v - removed inpadff, outpadff, bipadiff, bipadoff and bipadioff definitions

Signed-off-by: Rakesh Moolacheri <rakeshm@quicklogic.com>
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  3. Adding -family option in synth_quicklogic option 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  4. Updating cells map & sim files for pp3 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  5. Updating ap3 device support in yosys 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  6. Adding RAM/DSP as blackbox 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  7. LUT optimizations 

    QL: AP: tweak LUT costs to prefer bigger LUTs (Karol Gugala<kgugala@antmicro.com>)
QL: techmaps: split LUT techmaps for PP3 and AP3 (Karol Gugala<kgugala@antmicro.com>)
QL: AP3: set lut costs so LU4 is preferred one (Karol Gugala<kgugala@antmicro.com>)
QL: AP3: fix sim and map Verilogs (Karol Gugala<kgugala@antmicro.com>)

Signed-off-by: Karol Gugala <kgugala@antmicro.com>
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  8. Updating LUT1,2,3 cell mapping to LUT4 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  9. Adding io_reg related primitives 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  10. Update ap3_cells_sim.v 

    Signed-off-by: kkumar23 <61860672+kkumar23@users.noreply.github.com>
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  11. Adding adder support in ap3 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  12. Added techmaps for DFFE, split LUT and FF techmaps into separate files. 

    Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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  13. Updated the synth_quicklogic pass. 

    Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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  14. Adder support in AP3 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  15. Adder implementation where adder is inferred as carry+LUT4 instead of… 

    … one cell as add

Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  16. Separating LUT4 definition for PP3 & AP3 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  17. Merging changes from parent repo 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  18. Fixed synth_quicklogic flow to allow AP3 adder inference 

    Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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  19. Correcting indentation 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  20. Updating latch definition in cells_map file for AP3 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  21. Inferring adder as a cell - full_adder 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  22. Modify options to optimize lut utilization 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  23. Comment freduce 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  24. Adding nlutmap option 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  25. Adding lut optimization support for AP3 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  26. Removing commented code 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  27. Removing ap3_ff_map.v file and updating ap3_ffs_map.v file 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  28. Adding AP2 device support 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  29. Optimizing adder inference for AP3 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  30. Optimizing AP2 utilization 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  31. added support for infering and initialization of bram 

    Signed-off-by: Tarachand Pagarani <tpagarani@quicklogic.com>
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  32. abc lut option updated for ap2 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  33. ram init changes 

    Signed-off-by: Tarachand Pagarani <tpagarani@quicklogic.com>
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  34. add missing script 

    Signed-off-by: Tarachand Pagarani <tpagarani@quicklogic.com>
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  35. Changing lut option in abc for ap2 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  36. update lut option in abc command 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  37. Adding EQN property to LUT instance in edf 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  38. Adding optimizations to PP3 synthesis 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  39. Incorporating code review comments from Karol 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  40. Removing latch definition which is now defined in a separate file 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  41. Reverting lut option as suggested by Maciej 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  42. ram init updates 

    Signed-off-by: Tarachand Pagarani <tpagarani@quicklogic.com>
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  43. Modified the ram models to support initialization 

    Signed-off-by: Rakesh Moolacheri <rakeshm@quicklogic.com>
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  44. Reenabled LUT4 inference 

    Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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  45. correct the clock ports for RAM8k 

    Signed-off-by: Tarachand Pagarani <tpagarani@quicklogic.com>
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  46. modified to correct the yosys compilation error 

    Signed-off-by: Rakesh Moolacheri <rakeshm@quicklogic.com>
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  47. Updating copyright name 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  48. initialize bram primitives from hex file 

    Signed-off-by: Tarachand Pagarani <tpagarani@quicklogic.com>
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  49. update make file to remove FIFO and RAM block depedencies 

    Signed-off-by: Tarachand Pagarani <tpagarani@quicklogic.com>
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  50. change file parameters name 

    Signed-off-by: Tarachand Pagarani <tpagarani@quicklogic.com>
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  51. support RAM initialization 

    Signed-off-by: Rakesh Moolacheri <rakeshm@quicklogic.com>
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  52. map_bram is run only for PP3 as of now 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  53. Modified pp3_cells_sim.v file to support RAM init 

    Signed-off-by: Rakesh Moolacheri <rakeshm@quicklogic.com>
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  54. Adding cell mapping for _DFFSR_NPP_ & _DFFSR_PPP_ 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  55. change init file format for 16k block 

    Signed-off-by: Tarachand Pagarani <tpagarani@quicklogic.com>
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  56. adding d_buf inference 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  57. Adding review comments 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  58. Supporting d_buff inference for AP3 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  59. Adding io_map file for AP3 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  60. Infer clk port in in_reg or out_reg as ck_buff for AP3 & AP2 devices. 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  61. Adding external pad property to rst port 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  62. Rectifying clkbuf property on in_reg in AP2 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  63. Fixing an issue in RAM/DSP cell mapping 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  64. Updating in_reg/out_reg def in AP3. Replacing in_reg, out_reg with io… 

    …_reg in AP2

Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  65. Rectifying d_buff declaration issue 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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    Lalit Sharma authored and rw1nkler committed Oct 12, 2020
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  66. Fixing a compilation error in verilog 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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    Lalit Sharma authored and rw1nkler committed Oct 12, 2020
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  67. Changing QL_CARRY to full_adder for AP2 & AP3 device 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  68. Commenting redundant code 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  69. Replacing adder instance to full_adder for AP2, like AP3 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  70. Changing to uppercase for primitive cell names of AP3 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  71. Fix wrong rebase strategy remains 

    Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
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  72. Substitute YS_OVERRIDE with override 

    Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
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  73. Updating IO names to lower case 

    Signed-off-by: Lalit Sharma <lsharma@quicklogic.com>
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  74. Added additional ABC optimizations to synth_quicklogic 

    Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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  75. Allow less efficient use of BRAM resources 

    Before this change, yosys required 4096 bits (or at least 50%)
of the bits in a RAM to be used, in order to implement it as a
PB-RAM. Since there are less than 1000 FFs available in the FPGA
it means that any memory using somewhere between 1k and 4k bits
will not fit in the device.

This lowers the requirements on RAM efficiency to be more in line
with the iCE40 backend, which uses comparably sized FPGAs

Signed-off-by: Olof Kindgren <olof.kindgren@gmail.com>
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    olofk authored and rw1nkler committed Oct 12, 2020
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  76. Fix missing new lines and improve code formatting 

    Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
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    rw1nkler committed Oct 12, 2020
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