RISC-V Single and Double Precision Floating Point extension

CMakeLists.txt

@@ -124,7 +124,7 @@ FetchContent_MakeAvailable_Args(yaml-cpp EXCLUDE_FROM_ALL)
 option(SIMENG_ENABLE_TESTS "Whether to enable testing for SimEng" OFF)
 option(SIMENG_USE_EXTERNAL_LLVM "Use an external LLVM rather than building it as a submodule" OFF)
 option(SIMENG_SANITIZE "Enable compiler sanitizers" OFF)
-option(SIMENG_OPTIMIZE "Enable Extra Compiler Optimizatoins" OFF)
+option(SIMENG_OPTIMIZE "Enable Extra Compiler Optimizations" OFF)
 option(SIMENG_ENABLE_SST "Compile SimEng SST Wrapper" OFF)
 option(SIMENG_ENABLE_SST_TESTS "Enable testing for SST" OFF)
 
@@ -203,7 +203,7 @@ if(SIMENG_ENABLE_TESTS)
                  PATHS "${llvm_BINARY_DIR}/lib/cmake/llvm")
 
     # NOTE: we don't do the usual version checks here because it needs vars exported in find_LLVM
-    # we just assume it's good beacuse it must be whitelisted in FetchContent_Declare
+    # we just assume it's good because it must be whitelisted in FetchContent_Declare
 endif()
 
   set(SIMENG_LLVM_VERSION ${LLVM_VERSION_MAJOR} CACHE INTERNAL "LLVM major version number used.")

configs/DEMO_RISCV.yaml

@@ -7,11 +7,12 @@ Core:
   ISA: rv64
   Simulation-Mode: outoforder
   Clock-Frequency: 2.5
-  Fetch-Block-Size: 32
+  # Timer-Frequency is in MHz.
+  Timer-Frequency: 200
 Fetch:
   Fetch-Block-Size: 32
-  Loop-Buffer-Size: 0
-  Loop-Detection-Threshold: 0
+  Loop-Buffer-Size: 64
+  Loop-Detection-Threshold: 4
 Process-Image:
   Heap-Size: 1073741824
   Stack-Size: 1048576
@@ -20,7 +21,6 @@ Register-Set:
   FloatingPoint-Count: 90
 Pipeline-Widths:
   Commit: 4
-  Dispatch-Rate: 4
   FrontEnd: 4
   LSQ-Completion: 2
 Queue-Sizes:
@@ -31,10 +31,8 @@ Branch-Predictor:
   BTB-Tag-Bits: 11
   Saturating-Count-Bits: 2
   Global-History-Length: 10
-  RAS-entries: 1
+  RAS-entries: 5
   Fallback-Static-Predictor: "Always-Taken"
-  Branch-Predictor:
-  BTB-bitlength: 16
 L1-Data-Memory:
   Interface-Type: Fixed
 L1-Instruction-Memory:
@@ -53,10 +51,12 @@ Ports:
     Instruction-Support:
       - INT_SIMPLE
       - INT_MUL
+      - FLOAT
   1:
     Portname: Port 1
     Instruction-Support:
       - INT
+      - FLOAT
   2:
     Portname: Port 2
     Instruction-Support:
@@ -113,9 +113,29 @@ Latencies:
     Execution-Throughput: 1
   2:
     Instruction-Groups:
-      - INT_DIV
+      - INT_DIV_OR_SQRT
     Execution-Latency: 39
     Execution-Throughput: 39
+  3:
+    Instruction-Groups:
+      - FLOAT_SIMPLE_CMP
+    Execution-Latency: 5
+    Execution-Throughput: 1
+  4:
+    Instruction-Groups:
+      - FLOAT_MUL
+    Execution-Latency: 6
+    Execution-Throughput: 1
+  5:
+    Instruction-Groups:
+      - FLOAT_SIMPLE_CVT
+    Execution-Latency: 7
+    Execution-Throughput: 1
+  6:
+    Instruction-Groups:
+      - FLOAT_DIV_OR_SQRT
+    Execution-Latency: 16
+    Execution-Throughput: 16
 # CPU-Info mainly used to generate a replica of the special (or system) file directory
 # structure
 CPU-Info:
@@ -126,7 +146,7 @@ CPU-Info:
   Core-Count: 1
   # Socket-Count MUST be 1 as multi-socket simulations are not supported at this time. (TX2 true value is 2)
   Socket-Count: 1
-  # SMT MUST be 1 as Simultanious-Multi-Threading is not supported at this time. (TX2 true value is 4)
+  # SMT MUST be 1 as Simultaneous-Multi-Threading is not supported at this time. (TX2 true value is 4)
   SMT: 1
   # Below are the values needed to generate /proc/cpuinfo
   BogoMIPS: 400.00

configs/sst-cores/a64fx-sst.yaml

@@ -255,7 +255,7 @@ CPU-Info:
   Core-Count: 1
   # Socket-Count MUST be 1 as multi-socket simulations are not supported at this time. (A64FX true value is 1)
   Socket-Count: 1
-  # SMT MUST be 1 as Simultanious-Multi-Threading is not supported at this time. (A64FX true value is 1)
+  # SMT MUST be 1 as Simultaneous-Multi-Threading is not supported at this time. (A64FX true value is 1)
   SMT: 1
   # Below are the values needed to generate /proc/cpuinfo
   BogoMIPS: 200.00

docs/sphinx/developer/arch/supported/aarch64.rst

@@ -158,7 +158,7 @@ Also supported is the Arm SME extension and thus the use of ``ZA`` sub-tile regi
 
 SME instructions can also operate on sub-tile slices; individual rows or columns within a sub-tile. Regardless of whether a whole sub-tile or a slice is used as a source operand, all rows associated with said tile will be added to the ``operands`` vector. There are two reasons for this. First, the index value pointing to the relevant slice cannot be evaluated before instruction execution, thus, all sub-tile rows need to be provided. Second, if the source slice is a vertical slice (or a column of the sub-tile) then an element from each row is needed to construct the correct output.
 
-Furthermore, a similar situation is present when a sub-tile slice is a destination operand. The ``results`` vector will expect a ``registerValue`` entry for each row of the targetted sub-tile, again due to the same two reasons listed previously. But, when a sub-tile slice is a destination operand, **all** associated rows of the sub-tile will also be added to the ``operands`` vector. Again, this is down to two key, similar reasons. First, when a destination is a sub-tile slice, we only want to update that row or column. As the we are unable to calculate which slice will be our destination before execution has commenced, all possible slices must be added to the ``results`` vector. If we were to not provide a ``RegisterValue`` to each entry of the ``results`` vector, the default value is 0. Therefore, in order to not zero-out the other slices within the sub-tile we will need access to their current values. Secondly, if the destination is a vertical slice (or sub-tile column) then only one element per row should be updated; the rest should remain unchanged.
+Furthermore, a similar situation is present when a sub-tile slice is a destination operand. The ``results`` vector will expect a ``registerValue`` entry for each row of the targeted sub-tile, again due to the same two reasons listed previously. But, when a sub-tile slice is a destination operand, **all** associated rows of the sub-tile will also be added to the ``operands`` vector. Again, this is down to two key, similar reasons. First, when a destination is a sub-tile slice, we only want to update that row or column. As the we are unable to calculate which slice will be our destination before execution has commenced, all possible slices must be added to the ``results`` vector. If we were to not provide a ``RegisterValue`` to each entry of the ``results`` vector, the default value is 0. Therefore, in order to not zero-out the other slices within the sub-tile we will need access to their current values. Secondly, if the destination is a vertical slice (or sub-tile column) then only one element per row should be updated; the rest should remain unchanged.
 
 Before implementing any further SME functionality we highly recommend familiarising yourself with the specification; found `here <https://developer.arm.com/documentation/ddi0616/latest>`_.
 

src/include/simeng/FixedLatencyMemoryInterface.hh

@@ -57,7 +57,7 @@ class FixedLatencyMemoryInterface : public MemoryInterface {
   /** Clear the completed reads. */
   void clearCompletedReads() override;
 
-  /** Returns true if there are any oustanding memory requests in-flight. */
+  /** Returns true if there are any outstanding memory requests in-flight. */
   bool hasPendingRequests() const override;
 
   /** Tick the memory model to process the request queue. */

src/include/simeng/FlatMemoryInterface.hh

@@ -27,7 +27,7 @@ class FlatMemoryInterface : public MemoryInterface {
   /** Clear the completed reads. */
   void clearCompletedReads() override;
 
-  /** Returns true if there are any oustanding memory requests in-flight. */
+  /** Returns true if there are any outstanding memory requests in-flight. */
   bool hasPendingRequests() const override;
 
   /** Tick: do nothing */

src/include/simeng/Instruction.hh

@@ -24,7 +24,7 @@ class Instruction {
   bool exceptionEncountered() const;
 
   /** Retrieve the source registers this instruction reads. */
-  virtual const span<Register> getOperandRegisters() const = 0;
+  virtual const span<Register> getSourceRegisters() const = 0;
 
   /** Retrieve the data contained in the source registers this instruction
    * reads.*/

src/include/simeng/MemoryInterface.hh

@@ -63,7 +63,7 @@ class MemoryInterface {
   /** Clear the completed reads. */
   virtual void clearCompletedReads() = 0;
 
-  /** Returns true if there are any oustanding memory requests in-flight. */
+  /** Returns true if there are any outstanding memory requests in-flight. */
   virtual bool hasPendingRequests() const = 0;
 
   /** Tick the memory interface to allow it to process internal tasks.

src/include/simeng/RegisterValue.hh

@@ -90,7 +90,7 @@ class RegisterValue {
    * the specified datatype. */
   template <class T>
   const T* getAsVector() const {
-    static_assert(alignof(T) <= 8 && "Alignment over 8 bytes not guranteed");
+    static_assert(alignof(T) <= 8 && "Alignment over 8 bytes not guaranteed");
     assert(bytes > 0 && "Attempted to access an uninitialised RegisterValue");
     assert(sizeof(T) <= bytes &&
            "Attempted to access a RegisterValue as a datatype larger than the "

src/include/simeng/arch/aarch64/Instruction.hh

@@ -224,6 +224,7 @@ enum class InstructionException {
   EncodingUnallocated,
   EncodingNotYetImplemented,
   ExecutionNotYetImplemented,
+  AliasNotYetImplemented,
   MisalignedPC,
   DataAbort,
   SupervisorCall,
@@ -277,7 +278,7 @@ class Instruction : public simeng::Instruction {
   virtual InstructionException getException() const;
 
   /** Retrieve the source registers this instruction reads. */
-  const span<Register> getOperandRegisters() const override;
+  const span<Register> getSourceRegisters() const override;
 
   /** Retrieve the data contained in the source registers this instruction
    * reads.*/

src/include/simeng/arch/aarch64/MicroDecoder.hh

@@ -20,7 +20,7 @@ struct OpType {
  */
 class MicroDecoder {
  public:
-  /** Construct a micro decoder for splitting relevant instructons. */
+  /** Construct a micro decoder for splitting relevant instructions. */
   MicroDecoder(YAML::Node config);
   ~MicroDecoder();
 
@@ -73,7 +73,7 @@ class MicroDecoder {
 
   /** A micro-decoding cache, mapping an instruction word to a previously split
    * instruction. Instructions are added to the cache as they're split into
-   * their repsective micro-operations, to reduce the overhead of future
+   * their respective micro-operations, to reduce the overhead of future
    * splitting. */
   static std::unordered_map<uint32_t, std::vector<Instruction>>
       microDecodeCache;

src/include/simeng/arch/aarch64/helpers/float.hh

@@ -138,7 +138,7 @@ class floatHelp {
    * D represents the destination vector register type (e.g. for dd, D =
    * double).
    * N represents the source vector register type (e.g. for wn, N = int32_t).
-   * Returns correctly formated RegisterValue. */
+   * Returns correctly formatted RegisterValue. */
   template <typename D, typename N>
   static RegisterValue scvtf_FixedPoint(
       std::vector<RegisterValue>& operands,

src/include/simeng/arch/riscv/Architecture.hh

@@ -14,6 +14,19 @@ namespace simeng {
 namespace arch {
 namespace riscv {
 
+// A temporary enum to hold system register addresses
+// TODO this should be removed upon relevant capstone updates
+typedef enum riscv_sysreg {
+  RISCV_SYSREG_FFLAGS = 0x001,
+  RISCV_SYSREG_FRM = 0x002,
+  RISCV_SYSREG_FCSR = 0x003,
+
+  RISCV_SYSREG_CYCLE = 0xC00,
+  RISCV_SYSREG_TIME = 0xC01,
+  RISCV_SYSREG_INSTRET = 0xC02,
+
+} riscv_sysreg;
+
 /* A basic RISC-V implementation of the `Architecture` interface. */
 class Architecture : public arch::Architecture {
  public:
@@ -95,6 +108,9 @@ class Architecture : public arch::Architecture {
 
   /** A reference to a Linux kernel object to forward syscalls to. */
   kernel::Linux& linux_;
+
+  /** System Register of Processor Cycle Counter. */
+  simeng::Register cycleSystemReg_;
 };
 
 }  // namespace riscv

src/include/simeng/arch/riscv/Instruction.hh

@@ -1,6 +1,8 @@
 #pragma once
 
 #include <array>
+#include <cfenv>
+#include <functional>
 #include <unordered_map>
 
 #include "simeng/BranchPredictor.hh"
@@ -42,12 +44,15 @@ enum class InstructionException {
   EncodingUnallocated,
   EncodingNotYetImplemented,
   ExecutionNotYetImplemented,
+  AliasNotYetImplemented,
   MisalignedPC,
   DataAbort,
   SupervisorCall,
   HypervisorCall,
   SecureMonitorCall,
-  NoAvailablePort
+  NoAvailablePort,
+  IllegalInstruction,
+  PipelineFlush
 };
 
 /** A basic RISC-V implementation of the `Instruction` interface. */
@@ -58,12 +63,6 @@ class Instruction : public simeng::Instruction {
   Instruction(const Architecture& architecture,
               const InstructionMetadata& metadata);
 
-  /** Construct an instruction instance by decoding a provided instruction word.
-   */
-  Instruction(const Architecture& architecture,
-              const InstructionMetadata& metadata, uint8_t latency,
-              uint8_t stallCycles);
-
   /** Construct an instruction instance that raises an exception. */
   Instruction(const Architecture& architecture,
               const InstructionMetadata& metadata,
@@ -74,7 +73,7 @@ class Instruction : public simeng::Instruction {
   virtual InstructionException getException() const;
 
   /** Retrieve the source registers this instruction reads. */
-  const span<Register> getOperandRegisters() const override;
+  const span<Register> getSourceRegisters() const override;
 
   /** Retrieve the data contained in the source registers this instruction
    * reads.*/
@@ -149,6 +148,9 @@ class Instruction : public simeng::Instruction {
   /** Is this an atomic instruction? */
   bool isAtomic() const;
 
+  /** Is this a floating point operation? */
+  bool isFloat() const;
+
   /** Retrieve the instruction group this instruction belongs to. */
   uint16_t getGroup() const override;
 
@@ -162,19 +164,22 @@ class Instruction : public simeng::Instruction {
   /** Retrieve the instruction's metadata. */
   const InstructionMetadata& getMetadata() const;
 
+  /** Retrieve the instruction's associated architecture. */
+  const Architecture& getArchitecture() const;
+
   /** A special register value representing the zero register. If passed to
    * `setSourceRegisters`/`setDestinationRegisters`, the value will be
    * automatically supplied as zero. */
   static const Register ZERO_REGISTER;
 
- private:
   /** The maximum number of source registers any supported RISC-V instruction
    * can have. */
-  static const uint8_t MAX_SOURCE_REGISTERS = 2;
+  static const uint8_t MAX_SOURCE_REGISTERS = 3;
   /** The maximum number of destination registers any supported RISC-V
    * instruction can have. */
   static const uint8_t MAX_DESTINATION_REGISTERS = 1;
 
+ private:
   /** A reference to the ISA instance this instruction belongs to. */
   const Architecture& architecture_;
 
@@ -207,13 +212,6 @@ class Instruction : public simeng::Instruction {
    * registers. */
   void decode();
 
-  /** Invalidate instructions that are currently not yet implemented. This
- prevents errors during speculated branches with unknown destinations;
- non-executable assertions. memory is decoded into valid but not implemented
- instructions tripping assertions.
- TODO remove once all extensions are supported*/
-  void invalidateIfNotImplemented();
-
   // Scheduling
   /** The number of operands that have not yet had values supplied. Used to
    * determine execution readiness. */
@@ -223,6 +221,13 @@ class Instruction : public simeng::Instruction {
   /** Generate an ExecutionNotYetImplemented exception. */
   void executionNYI();
 
+  /** For instructions with a valid rm field, extract the rm value and change
+   * the CPP rounding mode accordingly, then call the function "operation"
+   * before reverting the CPP rounding mode to its initial value. "Operation"
+   * should contain the entire execution logic of the instruction
+   */
+  void setStaticRoundingModeThen(std::function<void(void)> operation);
+
   // Metadata
   /** Is this a store operation? */
   bool isStore_ = false;
@@ -242,6 +247,10 @@ class Instruction : public simeng::Instruction {
   bool isLogical_ = false;
   /** Is this a compare instruction? */
   bool isCompare_ = false;
+  /** Is this a floating point operation? */
+  bool isFloat_ = false;
+  /** Is this a floating point <-> integer convert operation? */
+  bool isConvert_ = false;
 
   // Memory
   /** Set the accessed memory addresses, and create a corresponding memory data