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Add AMD PMC/U support #222

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merged 5 commits into from
Aug 9, 2024
Merged

Add AMD PMC/U support #222

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411112c
Add AMD PMC/U support
lancelui-amzn Aug 6, 2024
b823522
clearer event labels, fixed l3 misses
lancelui-amzn Aug 7, 2024
5cc4e58
sum backend stall counters on milan
lancelui-amzn Aug 7, 2024
82c2f8f
rustfmt change
lancelui-amzn Aug 7, 2024
d1ee8e0
rename stall backend on milan
lancelui-amzn Aug 8, 2024
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4 changes: 2 additions & 2 deletions src/data/amd_genoa_perf_events.rs
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
use crate::data::perf_stat::{NamedCtr, NamedTypeCtr, PerfType};

static STALL_BACKEND_PKC: NamedTypeCtr = NamedTypeCtr {
static STALL_BACKEND: NamedTypeCtr = NamedTypeCtr {
perf_type: PerfType::RAW,
name: "Backend-Stalls",
config: 0x100001ea0,
Expand All @@ -15,7 +15,7 @@ lazy_static! {
pub static ref GENOA_CTRS: Vec<NamedCtr<'static>> = [
NamedCtr {
name: "stall_backend_pkc",
nrs: vec![STALL_BACKEND_PKC],
nrs: vec![STALL_BACKEND],
drs: vec![CYCLES],
scale: 167 //~= 1000/6
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That is really weird, why this value instead of just 1000? The ones below for milan are just 1000.

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Not sure, I think its from each cycle being able to dispatch 6 instructions? This scale was from our documentation and AMD documentation.

},
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8 changes: 4 additions & 4 deletions src/data/amd_milan_perf_events.rs
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Original file line number Diff line number Diff line change
@@ -1,11 +1,11 @@
use crate::data::perf_stat::{NamedCtr, NamedTypeCtr, PerfType};

static STALL_BACKEND_PKC1: NamedTypeCtr = NamedTypeCtr {
static STALL_BACKEND_1: NamedTypeCtr = NamedTypeCtr {
perf_type: PerfType::RAW,
name: "Backend-Stalls-1",
config: 0xf7ae,
};
static STALL_BACKEND_PKC2: NamedTypeCtr = NamedTypeCtr {
static STALL_BACKEND_2: NamedTypeCtr = NamedTypeCtr {
perf_type: PerfType::RAW,
name: "Backend-Stalls-2",
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Are there any better specifiers for these besides just -1 and -2?

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Not sure, each one counts several backend stall types.

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If it's not documented what exactly each one counts, perhaps the better thing to do is add them together. That assumes there's not overlap in what each one counts.

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@lancelui-amzn lancelui-amzn Aug 7, 2024 •
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Talked with Geoff, the sum of the two is the total backend stalls. Pushed changes

config: 0x27af,
Expand All @@ -20,13 +20,13 @@ lazy_static! {
pub static ref MILAN_CTRS: Vec<NamedCtr<'static>> = [
NamedCtr {
name: "stall_backend_pkc1",
nrs: vec![STALL_BACKEND_PKC1],
nrs: vec![STALL_BACKEND_1],
drs: vec![CYCLES],
scale: 1000
},
NamedCtr {
name: "stall_backend_pkc2",
nrs: vec![STALL_BACKEND_PKC2],
nrs: vec![STALL_BACKEND_2],
drs: vec![CYCLES],
scale: 1000
},
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61 changes: 31 additions & 30 deletions src/data/amd_perf_events.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -11,54 +11,55 @@ static CYCLES: NamedTypeCtr = NamedTypeCtr {
name: "Cycles",
config: 0x0076,
};
static BRANCHES: NamedTypeCtr = NamedTypeCtr {
static BRANCH_MISPRED: NamedTypeCtr = NamedTypeCtr {
perf_type: PerfType::RAW,
name: "Branches",
name: "Branch-Mispredictions",
config: 0x00c3,
};
static L1_DATA: NamedTypeCtr = NamedTypeCtr {
static L1_DATA_FILL: NamedTypeCtr = NamedTypeCtr {
perf_type: PerfType::RAW,
name: "L1-Data",
name: "L1-Data-Fills",
config: 0xff44,
};
static L1_INSTRUCTIONS: NamedTypeCtr = NamedTypeCtr {
static L1_INSTRUCTION_MISS: NamedTypeCtr = NamedTypeCtr {
perf_type: PerfType::RAW,
name: "L1-Instructions",
name: "L1-Instruction-Misses",
config: 0x1060,
};
static L2: NamedTypeCtr = NamedTypeCtr {
static L2_DEMAND_MISS: NamedTypeCtr = NamedTypeCtr {
perf_type: PerfType::RAW,
name: "L2",
name: "L2-Demand-Misses",
config: 0x0964,
};
static L3: NamedTypeCtr = NamedTypeCtr {
static L1_ANY_FILLS_DRAM: NamedTypeCtr = NamedTypeCtr {
// Approximately L3 Misses
perf_type: PerfType::RAW,
name: "L3",
config: 0x0843,
name: "L1-Any-Fills-DRAM",
config: 0x0844,
};
static STALL_FRONTEND_PKC: NamedTypeCtr = NamedTypeCtr {
static STALL_FRONTEND: NamedTypeCtr = NamedTypeCtr {
perf_type: PerfType::RAW,
name: "Frontend-Stalls",
config: 0x00a9,
};
static INSTRUCTION_TLB: NamedTypeCtr = NamedTypeCtr {
static INSTRUCTION_TLB_MISS: NamedTypeCtr = NamedTypeCtr {
perf_type: PerfType::RAW,
name: "Instruction-TLB",
name: "Instruction-TLB-Misses",
config: 0x0084,
};
static INSTRUCTION_TLB_TW: NamedTypeCtr = NamedTypeCtr {
static INSTRUCTION_TLB_TW_MISS: NamedTypeCtr = NamedTypeCtr {
perf_type: PerfType::RAW,
name: "Instruction-TLB-TW",
name: "Instruction-TLB-TW-Misses",
config: 0x0f85,
};
static DATA_TLB: NamedTypeCtr = NamedTypeCtr {
static DATA_TLB_MISS: NamedTypeCtr = NamedTypeCtr {
perf_type: PerfType::RAW,
name: "Data-TLB",
name: "Data-TLB-Misses",
config: 0xff45,
};
static DATA_TLB_TW: NamedTypeCtr = NamedTypeCtr {
static DATA_TLB_TW_MISS: NamedTypeCtr = NamedTypeCtr {
perf_type: PerfType::RAW,
name: "Data-TLB-TW",
name: "Data-TLB-TW-Misses",
config: 0xf045,
};

Expand All @@ -72,61 +73,61 @@ lazy_static! {
},
NamedCtr {
name: "branch-mpki",
nrs: vec![BRANCHES],
nrs: vec![BRANCH_MISPRED],
drs: vec![INSTRUCTIONS],
scale: 1000
},
NamedCtr {
name: "data-l1-mpki",
nrs: vec![L1_DATA],
nrs: vec![L1_DATA_FILL],
drs: vec![INSTRUCTIONS],
scale: 1000
},
NamedCtr {
name: "inst-l1-mpki",
nrs: vec![L1_INSTRUCTIONS],
nrs: vec![L1_INSTRUCTION_MISS],
drs: vec![INSTRUCTIONS],
scale: 1000
},
NamedCtr {
name: "l2-mpki",
nrs: vec![L2],
nrs: vec![L2_DEMAND_MISS],
drs: vec![INSTRUCTIONS],
scale: 1000
},
NamedCtr {
name: "l3-mpki",
nrs: vec![L3],
nrs: vec![L1_ANY_FILLS_DRAM],
drs: vec![INSTRUCTIONS],
scale: 1000
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Name says L3, nrs says L1. Are you sure this is right?

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The counter is approximating L3 misses. "This is sorta l3 mpki, but ellides Prefetch misses from L2" - from our docs.

},
NamedCtr {
name: "stall_frontend_pkc",
nrs: vec![STALL_FRONTEND_PKC],
nrs: vec![STALL_FRONTEND],
drs: vec![CYCLES],
scale: 1000
},
NamedCtr {
name: "inst-tlb-mpki",
nrs: vec![INSTRUCTION_TLB],
nrs: vec![INSTRUCTION_TLB_MISS],
drs: vec![INSTRUCTIONS],
scale: 1000
},
NamedCtr {
name: "inst-tlb-tw-mpki",
nrs: vec![INSTRUCTION_TLB_TW],
nrs: vec![INSTRUCTION_TLB_TW_MISS],
drs: vec![INSTRUCTIONS],
scale: 1000
},
NamedCtr {
name: "data-tlb-mpki",
nrs: vec![DATA_TLB],
nrs: vec![DATA_TLB_MISS],
drs: vec![INSTRUCTIONS],
scale: 1000
},
NamedCtr {
name: "data-tlb-tw-pki",
nrs: vec![DATA_TLB_TW],
nrs: vec![DATA_TLB_TW_MISS],
drs: vec![INSTRUCTIONS],
scale: 1000
},
Expand Down
4 changes: 2 additions & 2 deletions src/data/perf_stat.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -146,9 +146,9 @@ impl CollectData for PerfStatRaw {
perf_list = amd_perf_events::PERF_LIST.to_vec();

/* Get Model specific events */
platform_specific_counter = match cpu_info.model_name.as_str() {
platform_specific_counter = match cpu_info.model_name.get(..13).unwrap_or_default() {
"AMD EPYC 9R14" => GENOA_CTRS.to_vec(),
"AMD EPYC 7R13 Processor" => MILAN_CTRS.to_vec(),
"AMD EPYC 7R13" => MILAN_CTRS.to_vec(),
_ => Vec::new(),
};
} else {
Expand Down
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