liteeth/mac/sram: Switch to LiteXModule.

liteeth/mac/sram.py

@@ -9,14 +9,16 @@
 
 import math
 
+from litex.gen import *
+
 from liteeth.common import *
 
 from litex.soc.interconnect.csr import *
 from litex.soc.interconnect.csr_eventmanager import *
 
 # MAC SRAM Writer ----------------------------------------------------------------------------------
 
-class LiteEthMACSRAMWriter(Module, AutoCSR):
+class LiteEthMACSRAMWriter(LiteXModule):
     def __init__(self, dw, depth, nslots=2, endianness="big", timestamp=None):
         # Endpoint / Signals.
         self.sink      = sink = stream.Endpoint(eth_phy_description(dw))
@@ -38,7 +40,7 @@ def __init__(self, dw, depth, nslots=2, endianness="big", timestamp=None):
             self._timestamp = CSRStatus(timestampbits)
 
         # Event Manager.
-        self.submodules.ev = EventManager()
+        self.ev = EventManager()
         self.ev.available  = EventSourceLevel()
         self.ev.finalize()
 
@@ -70,10 +72,10 @@ def __init__(self, dw, depth, nslots=2, endianness="big", timestamp=None):
         stat_fifo_layout = [("slot", slotbits), ("length", lengthbits)]
         if timestamp is not None:
             stat_fifo_layout += [("timestamp", timestampbits)]
-        self.submodules.stat_fifo = stat_fifo = stream.SyncFIFO(stat_fifo_layout, nslots)
+        self.stat_fifo = stat_fifo = stream.SyncFIFO(stat_fifo_layout, nslots)
 
         # FSM.
-        self.submodules.fsm = fsm = FSM(reset_state="WRITE")
+        self.fsm = fsm = FSM(reset_state="WRITE")
         fsm.act("WRITE",
             If(sink.valid,
                 If(stat_fifo.sink.ready,
@@ -193,7 +195,7 @@ def __init__(self, dw, depth, nslots=2, endianness="big", timestamp=None):
             self._timestamp      = CSRStatus(timestampbits)
 
         # Event Manager.
-        self.submodules.ev = EventManager()
+        self.ev = EventManager()
         self.ev.done       = EventSourcePulse() if timestamp is None else EventSourceLevel()
         self.ev.finalize()
 
@@ -238,7 +240,7 @@ def __init__(self, dw, depth, nslots=2, endianness="big", timestamp=None):
         )
 
         # FSM.
-        self.submodules.fsm = fsm = FSM(reset_state="IDLE")
+        self.fsm = fsm = FSM(reset_state="IDLE")
         fsm.act("IDLE",
             If(cmd_fifo.source.valid,
                 read.eq(1),
@@ -302,7 +304,7 @@ def __init__(self, dw, depth, nslots=2, endianness="big", timestamp=None):
 
 class LiteEthMACSRAM(Module, AutoCSR):
     def __init__(self, dw, depth, nrxslots, ntxslots, endianness, timestamp=None):
-        self.submodules.writer = LiteEthMACSRAMWriter(dw, depth, nrxslots, endianness, timestamp)
-        self.submodules.reader = LiteEthMACSRAMReader(dw, depth, ntxslots, endianness, timestamp)
-        self.submodules.ev     = SharedIRQ(self.writer.ev, self.reader.ev)
+        self.writer = LiteEthMACSRAMWriter(dw, depth, nrxslots, endianness, timestamp)
+        self.reader = LiteEthMACSRAMReader(dw, depth, ntxslots, endianness, timestamp)
+        self.ev     = SharedIRQ(self.writer.ev, self.reader.ev)
         self.sink, self.source = self.writer.sink, self.reader.source