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[docs] Fix broken image links in docs
Build and Test #27443: Pull request #7710 opened by Ivecia
October 16, 2024 08:20 Action required Ivecia:main
October 16, 2024 08:20 Action required
[Verif] Add LowerFormalToHW pass (#7707)
Build and Test #27442: Commit ea952ba pushed by leonardt
October 16, 2024 00:04 14m 42s main
October 16, 2024 00:04 14m 42s
[Verif] Add LowerFormalToHW pass
Build and Test #27441: Pull request #7707 synchronize by leonardt
October 15, 2024 21:53 26m 32s dev/lenny/verif-formal-export-verilog
October 15, 2024 21:53 26m 32s
[arcilator] Add clock divider integration test
Build and Test #27440: Pull request #7705 synchronize by fabianschuiki
October 15, 2024 21:50 13m 46s fschuiki/arc-remove-legalization
October 15, 2024 21:50 13m 46s
[arcilator] Add clock divider integration test
Build and Test #27437: Pull request #7705 synchronize by fabianschuiki
October 15, 2024 21:50 25m 31s fschuiki/arc-remove-legalization
October 15, 2024 21:50 25m 31s
[FIRRTL] Don't force non-local trackers in Dedup.
Build and Test #27435: Pull request #7709 synchronize by mikeurbach
October 15, 2024 21:29 16m 16s mikeurbach/dedup-local-paths
October 15, 2024 21:29 16m 16s
[FIRRTL] Don't force non-local trackers in Dedup.
Build and Test #27434: Pull request #7709 opened by mikeurbach
October 15, 2024 20:24 31m 58s mikeurbach/dedup-local-paths
October 15, 2024 20:24 31m 58s
[Verif] Add LowerFormalToHW pass
Build and Test #27433: Pull request #7707 synchronize by leonardt
October 15, 2024 18:42 41s dev/lenny/verif-formal-export-verilog
October 15, 2024 18:42 41s
[Arc] Add dominance-aware pass to sink ops and merge scf.if ops (#7702)
Build and Test #27432: Commit 2085d0d pushed by fabianschuiki
October 15, 2024 18:38 14m 28s main
October 15, 2024 18:38 14m 28s
[Verif] Add LowerFormalToHW pass
Build and Test #27431: Pull request #7707 synchronize by leonardt
October 15, 2024 18:35 13m 48s dev/lenny/verif-formal-export-verilog
October 15, 2024 18:35 13m 48s
[Verif] Add LowerFormalToHW pass
Build and Test #27430: Pull request #7707 synchronize by leonardt
October 15, 2024 18:33 14m 58s dev/lenny/verif-formal-export-verilog
October 15, 2024 18:33 14m 58s
[Verif] Add LowerFormalToHW pass
Build and Test #27429: Pull request #7707 synchronize by leonardt
October 15, 2024 17:48 26m 21s dev/lenny/verif-formal-export-verilog
October 15, 2024 17:48 26m 21s
[arcilator] Add clock divider integration test
Build and Test #27425: Pull request #7705 synchronize by fabianschuiki
October 15, 2024 17:18 27m 46s fschuiki/arc-remove-legalization
October 15, 2024 17:18 27m 46s
[arcilator] Add clock divider integration test
Build and Test #27424: Pull request #7705 synchronize by fabianschuiki
October 15, 2024 17:18 31m 0s fschuiki/arc-remove-legalization
October 15, 2024 17:18 31m 0s
[Arc] Add dominance-aware pass to sink ops and merge scf.if ops
Build and Test #27422: Pull request #7702 synchronize by fabianschuiki
October 15, 2024 17:18 27m 34s fschuiki/arc-merge-ifs
October 15, 2024 17:18 27m 34s
[Verif] Add LowerFormalToHW pass
Build and Test #27421: Pull request #7707 synchronize by leonardt
October 15, 2024 17:02 32m 41s dev/lenny/verif-formal-export-verilog
October 15, 2024 17:02 32m 41s
[Verif] Add LowerFormalToHW pass
Build and Test #27420: Pull request #7707 synchronize by leonardt
October 15, 2024 17:00 28m 29s dev/lenny/verif-formal-export-verilog
October 15, 2024 17:00 28m 29s
[arcilator] Add clock divider integration test
Build and Test #27419: Pull request #7705 synchronize by fabianschuiki
October 15, 2024 16:47 33m 23s fschuiki/arc-remove-legalization
October 15, 2024 16:47 33m 23s