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[ExportVerilog] Don't generate automatic variable
if the tool doesn't support it
#1633
Comments
IMO, it would be much more hardware engineer-friendly verilog emitter if it can place all wire, reg, logic varlable at the start of the module. :) |
Sure, people will be able to pass the flag to get that behavior if they want. |
I think the above spilling outside the always block will result in flip flops being created for wire _T_12 = _T_2 & ~(|a_first_counter);
wire _T_13 = _T_3 & ~(|d_first_counter);
always @(posedge clock) begin
/* ... */
end @drom: thoughts about above? The mixing of blocking and non-blocking assignments inside the Basically, there's no great solution here because Anything that you try here, you may want to run through both of:
This will give you some feedback on whether or not the output makes sense. 😄 |
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I can't find any way to support this in a reasonable way: icarus and yosys don't support assigning to wires declared at top level in an always block. Neither supports |
I believe I can just spill all of the expressions to the top level as wire decls. That is gross, but will be functional. I'll take care of this. |
This is actually really nasty, we need to emit
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Sounds like the heuristic is:
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…ion. This is the first step to supporting verilog implementations like Yosys and Icarus Verilog that don't support SystemVerilog "automatic logic" variables in procedural scopes. For this step we handle side effecting operations (like the RANDOM macros in FIRRTL lowering) by spilling them to a local reg with a blocking assignment, the same way SFC does. This is one step towards resolving Issue #1633
According to this thread, Yosys doesn't support
automatic logic
values in an always block. We generate these when spilling into new declarations due to overly long line length, and when things are multiply used in always blocks. Here's an example from the thread:It is suggested that the verilog printer inject top level declarations like so:
This should only be done under a
LoweringOptions
flag.The text was updated successfully, but these errors were encountered: