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"reg" is invalid Verilog identifier #2

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drom opened this issue Apr 30, 2020 · 2 comments
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"reg" is invalid Verilog identifier #2

drom opened this issue Apr 30, 2020 · 2 comments
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bug Something isn't working ExportVerilog
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SiFive-1

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@drom
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drom commented Apr 30, 2020

Like many other Verilog keywords, reg is an invalid identifier.

https://github.com/sifive/clattner-experimental/blob/d231ef24235ce132fd93c313771c56888161e482/test/EmitVerilog/verilog-basic.fir#L343
lattner added a commit that referenced this issue May 1, 2020
@lattner
[EmitVerilog] Make sure the Verilog emitter avoids using reserved
2ae4d2c 
words and other identifiers that cause problems.  This fixes
Issue #2.
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lattner commented May 1, 2020

Fixed in bb7195b, thank you!

@lattner lattner closed this as completed May 1, 2020
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lattner commented May 1, 2020

Sorry, I meant 2ae4d2c

@drom drom added the FIRRTL Involving the `firrtl` dialect label Jul 14, 2020
@stellaraccident stellaraccident mentioned this issue Nov 6, 2020
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@stephenneuendorffer stephenneuendorffer mentioned this issue Nov 21, 2020
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@lattner lattner mentioned this issue Dec 10, 2020
Merged
@teqdruid teqdruid mentioned this issue Dec 29, 2020
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@lattner lattner mentioned this issue Dec 30, 2020
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@lattner lattner mentioned this issue Jan 10, 2021
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@drom drom modified the milestone: SiFive-1 Mar 23, 2021
@darthscsi darthscsi added this to the SiFive-1 milestone Apr 7, 2021
@darthscsi darthscsi added bug Something isn't working ExportVerilog and removed FIRRTL Involving the `firrtl` dialect labels Apr 7, 2021
@lattner lattner mentioned this issue Jul 13, 2021
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@lattner lattner mentioned this issue Aug 29, 2021
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mortbopet added a commit to mortbopet/circt that referenced this issue Sep 17, 2021
@mortbopet
[Handshake] Address review comments llvm#2
0e6ef1c
@lattner lattner mentioned this issue Oct 5, 2021
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This was referenced May 12, 2022
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mortbopet added a commit that referenced this issue Sep 16, 2022
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# This is a combination of 2 commits.
b61f9ed 
# This is the 1st commit message:

[Pipeline] Add pipeline stage register materialization pass

This commit adds an intermediate transformation to the Pipeline dialect
which is responsible for converting `pipeline.stage` to `pipeline.stage.register`
operations. The purpose of this transformation is to 'fix' where
registers needs to be placed in the pipeline, after all stages have been
defined and placed.

In short, the transformation will scan through the pipeline (in order,
top to bottom) and insert `pipeline.stage.register` operations in place
of `pipeline.stage` operations. Any operand used in any operation will
be analyzed to determine if it originates in between the last seen stage
and the operation itself. If not, this means that the operand crossed
a pipeline stage, and as such, the value will be routed through the
predecessor stage (`routeThroughStage`).

# This is the commit message #2:

Tidy up
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