[firrtl] Add 4.0.0 public modules

include/circt/Dialect/FIRRTL/FIRParser.h

@@ -46,7 +46,7 @@ struct FIRParserOptions {
   /// This, along with numOMIRFiles provides structure to the buffers in the
   /// source manager.
   unsigned numAnnotationFiles;
-  bool scalarizeTopModule = false;
+  bool scalarizePublicModules = false;
   bool scalarizeExtModules = false;
 };
 

lib/Dialect/FIRRTL/Import/FIRParser.cpp

@@ -4111,7 +4111,7 @@ struct FIRCircuitParser : public FIRParser {
   ParseResult parseExtClass(CircuitOp circuit, unsigned indent);
   ParseResult parseExtModule(CircuitOp circuit, unsigned indent);
   ParseResult parseIntModule(CircuitOp circuit, unsigned indent);
-  ParseResult parseModule(CircuitOp circuit, unsigned indent);
+  ParseResult parseModule(CircuitOp circuit, bool isPublic, unsigned indent);
 
   ParseResult parsePortList(SmallVectorImpl<PortInfo> &resultPorts,
                             SmallVectorImpl<SMLoc> &resultPortLocs,
@@ -4368,6 +4368,7 @@ ParseResult FIRCircuitParser::skipToModuleEnd(unsigned indent) {
     case FIRToken::kw_extmodule:
     case FIRToken::kw_intmodule:
     case FIRToken::kw_module:
+    case FIRToken::kw_public:
     case FIRToken::kw_layer:
     case FIRToken::kw_type:
       // All module declarations should have the same indentation
@@ -4497,6 +4498,7 @@ ParseResult FIRCircuitParser::parseClass(CircuitOp circuit, unsigned indent) {
   // build it
   auto builder = circuit.getBodyBuilder();
   auto classOp = builder.create<ClassOp>(info.getLoc(), name, portList);
+  classOp.setPrivate();
   deferredModules.emplace_back(
       DeferredModuleToParse{classOp, portLocs, getLexer().getCursor(), indent});
 
@@ -4569,13 +4571,20 @@ ParseResult FIRCircuitParser::parseExtModule(CircuitOp circuit,
     return failure();
 
   auto builder = circuit.getBodyBuilder();
-  auto convention = getConstants().options.scalarizeExtModules
-                        ? Convention::Scalarized
-                        : Convention::Internal;
+  auto isMainModule = (name == circuit.getName());
+  auto convention =
+      (isMainModule && getConstants().options.scalarizePublicModules) ||
+              getConstants().options.scalarizeExtModules
+          ? Convention::Scalarized
+          : Convention::Internal;
   auto conventionAttr = ConventionAttr::get(getContext(), convention);
   auto annotations = ArrayAttr::get(getContext(), {});
-  builder.create<FExtModuleOp>(info.getLoc(), name, conventionAttr, portList,
-                               defName, annotations, parameters, internalPaths);
+  auto extModuleOp = builder.create<FExtModuleOp>(
+      info.getLoc(), name, conventionAttr, portList, defName, annotations,
+      parameters, internalPaths);
+  auto visibility = isMainModule ? SymbolTable::Visibility::Public
+                                 : SymbolTable::Visibility::Private;
+  SymbolTable::setSymbolVisibility(extModuleOp, visibility);
   return success();
 }
 
@@ -4609,13 +4618,16 @@ ParseResult FIRCircuitParser::parseIntModule(CircuitOp circuit,
 
   ArrayAttr annotations = getConstants().emptyArrayAttr;
   auto builder = circuit.getBodyBuilder();
-  builder.create<FIntModuleOp>(info.getLoc(), name, portList, intName,
-                               annotations, parameters, internalPaths);
+  builder
+      .create<FIntModuleOp>(info.getLoc(), name, portList, intName, annotations,
+                            parameters, internalPaths)
+      .setPrivate();
   return success();
 }
 
 /// module ::= 'module' id ':' info? INDENT portlist simple_stmt_block DEDENT
-ParseResult FIRCircuitParser::parseModule(CircuitOp circuit, unsigned indent) {
+ParseResult FIRCircuitParser::parseModule(CircuitOp circuit, bool isPublic,
+                                          unsigned indent) {
   StringAttr name;
   SmallVector<PortInfo, 8> portList;
   SmallVector<SMLoc> portLocs;
@@ -4626,18 +4638,20 @@ ParseResult FIRCircuitParser::parseModule(CircuitOp circuit, unsigned indent) {
       info.parseOptionalInfo() || parsePortList(portList, portLocs, indent))
     return failure();
 
-  auto circuitName = circuit.getName();
-  auto isMainModule = (name == circuitName);
+  // The main module is implicitly public.
+  isPublic |= name == circuit.getName();
+
   ArrayAttr annotations = getConstants().emptyArrayAttr;
   auto convention = Convention::Internal;
-  if (isMainModule && getConstants().options.scalarizeTopModule)
+  if (isPublic && getConstants().options.scalarizePublicModules)
     convention = Convention::Scalarized;
   auto conventionAttr = ConventionAttr::get(getContext(), convention);
   auto builder = circuit.getBodyBuilder();
   auto moduleOp = builder.create<FModuleOp>(info.getLoc(), name, conventionAttr,
                                             portList, annotations);
-  auto visibility = isMainModule ? SymbolTable::Visibility::Public
-                                 : SymbolTable::Visibility::Private;
+
+  auto visibility = isPublic ? SymbolTable::Visibility::Public
+                             : SymbolTable::Visibility::Private;
   SymbolTable::setSymbolVisibility(moduleOp, visibility);
 
   // Parse the body of this module after all prototypes have been parsed. This
@@ -4671,7 +4685,14 @@ ParseResult FIRCircuitParser::parseToplevelDefinition(CircuitOp circuit,
       return failure();
     return parseLayer(circuit);
   case FIRToken::kw_module:
-    return parseModule(circuit, indent);
+    return parseModule(circuit, /*isPublic=*/false, indent);
+  case FIRToken::kw_public:
+    if (requireFeature({4, 0, 0}, "public modules"))
+      return failure();
+    consumeToken();
+    if (getToken().getKind() == FIRToken::kw_module)
+      return parseModule(circuit, /*isPublic=*/true, indent);
+    return emitError(getToken().getLoc(), "only modules may be public");
   case FIRToken::kw_type:
     return parseTypeDecl();
   default:
@@ -4935,6 +4956,7 @@ ParseResult FIRCircuitParser::parseCircuit(
     case FIRToken::kw_intmodule:
     case FIRToken::kw_layer:
     case FIRToken::kw_module:
+    case FIRToken::kw_public:
     case FIRToken::kw_type: {
       auto indent = getIndentation();
       if (!indent.has_value())
@@ -4986,14 +5008,6 @@ ParseResult FIRCircuitParser::parseCircuit(
            << "' must contain a module named '" << circuit.getName() << "'";
   }
 
-  // If the circuit has an entry point that is not an external module, set the
-  // visibility of all non-main modules to private.
-  if (auto mainMod = dyn_cast<FModuleOp>(*main)) {
-    for (auto mod : circuit.getOps<FModuleLike>()) {
-      if (mod != main)
-        SymbolTable::setSymbolVisibility(mod, SymbolTable::Visibility::Private);
-    }
-  }
   return success();
 }
 

lib/Dialect/FIRRTL/Import/FIRTokenKinds.def

@@ -139,6 +139,7 @@ TOK_KEYWORD(old)
 TOK_KEYWORD(output)
 TOK_KEYWORD(parameter)
 TOK_KEYWORD(propassign)
+TOK_KEYWORD(public)
 TOK_KEYWORD(rdwr)
 TOK_KEYWORD(read)
 TOK_KEYWORD(ref)

test/Dialect/FIRRTL/parse-basic.fir

@@ -1863,3 +1863,15 @@ circuit AnyRef:
     ; CHECK-NEXT: %[[CAST:.+]] = firrtl.object.anyref_cast %[[OBJ]]
     ; CHECK-NEXT: %[[LIST:.+]] = firrtl.list.create %[[CAST]], %x
     ; CHECK-NEXT: propassign %listOfAny, %[[LIST]]
+
+;// -----
+
+FIRRTL version 4.0.0
+; CHECK-LABEL: circuit "PublicModules"
+circuit PublicModules:
+  ; CHECK: firrtl.module @Foo
+  public module Foo:
+  ; CHECK: firrtl.module private @Bar
+  module Bar:
+  ; CHECK: firrtl.module @PublicModules
+  public module PublicModules:

test/Dialect/FIRRTL/parse-errors.fir

@@ -1140,3 +1140,16 @@ circuit DoubleRadix:
     output d : Double
     ; expected-error @below {{expected floating point in Double expression}}
     propassign d, Double(0hABC)
+
+;// -----
+FIRRTL version 3.9.0
+circuit PublicModuleUnsupported:
+  ; expected-error @below {{public modules are a FIRRTL 4.0.0+ feature}}
+  public module PublicModuleUnsupported:
+
+;// -----
+FIRRTL version 4.0.0
+circuit PublicNonModule:
+  ; expected-error @below {{only modules may be public}}
+  public extmodule Foo:
+  module PublicNonModule:

test/firtool/convention.fir

@@ -1,29 +1,29 @@
-; RUN: firtool %s --format=fir --parse-only --scalarize-top-module=false --scalarize-ext-modules=false --preserve-aggregate=all | FileCheck --check-prefix=SCALARIZE_NONE %s
-; RUN: firtool %s --format=fir --parse-only --scalarize-top-module=true  --scalarize-ext-modules=false --preserve-aggregate=all | FileCheck --check-prefix=SCALARIZE_TOP  %s
-; RUN: firtool %s --format=fir --parse-only --scalarize-top-module=false --scalarize-ext-modules=true  --preserve-aggregate=all | FileCheck --check-prefix=SCALARIZE_EXT  %s
-; RUN: firtool %s --format=fir --parse-only --scalarize-top-module=true  --scalarize-ext-modules=true  --preserve-aggregate=all | FileCheck --check-prefix=SCALARIZE_BOTH %s
+; RUN: firtool %s --format=fir --parse-only --scalarize-public-modules=false --scalarize-ext-modules=false --preserve-aggregate=all | FileCheck --check-prefix=SCALARIZE_NONE %s
+; RUN: firtool %s --format=fir --parse-only --scalarize-public-modules=true  --scalarize-ext-modules=false --preserve-aggregate=all | FileCheck --check-prefix=SCALARIZE_PUB  %s
+; RUN: firtool %s --format=fir --parse-only --scalarize-public-modules=false --scalarize-ext-modules=true  --preserve-aggregate=all | FileCheck --check-prefix=SCALARIZE_EXT  %s
+; RUN: firtool %s --format=fir --parse-only --scalarize-public-modules=true  --scalarize-ext-modules=true  --preserve-aggregate=all | FileCheck --check-prefix=SCALARIZE_BOTH %s
 
 ; Ensure that top module and ext modules are marked scalarized.
 
 circuit Top :
   ; SCALARIZE_NONE-NOT: attributes {convention = #firrtl<convention scalarized>}
-  ; SCALARIZE_TOP:      attributes {convention = #firrtl<convention scalarized>}
+  ; SCALARIZE_PUB:      attributes {convention = #firrtl<convention scalarized>}
   ; SCALARIZE_EXT-NOT:  attributes {convention = #firrtl<convention scalarized>}
   ; SCALARIZE_BOTH:     attributes {convention = #firrtl<convention scalarized>}
   module Top :
     output port: UInt<8>[2]
     port[0] <= UInt<8>(0)
     port[1] <= UInt<8>(0)
-  
+
   ; SCALARIZE_NONE-NOT: attributes {convention = #firrtl<convention scalarized>}
-  ; SCALARIZE_TOP-NOT:  attributes {convention = #firrtl<convention scalarized>}
+  ; SCALARIZE_PUB-NOT:  attributes {convention = #firrtl<convention scalarized>}
   ; SCALARIZE_EXT:      attributes {convention = #firrtl<convention scalarized>}
   ; SCALARIZE_BOTH:     attributes {convention = #firrtl<convention scalarized>}
   extmodule External :
     output port: UInt<8>[2]
 
   ; SCALARIZE_NONE-NOT: attributes {convention = #firrtl<convention scalarized>}
-  ; SCALARIZE_TOP-NOT:  attributes {convention = #firrtl<convention scalarized>}
+  ; SCALARIZE_PUB-NOT:  attributes {convention = #firrtl<convention scalarized>}
   ; SCALARIZE_EXT-NOT:  attributes {convention = #firrtl<convention scalarized>}
   ; SCALARIZE_BOTH-NOT: attributes {convention = #firrtl<convention scalarized>}
   module Internal :

test/firtool/refs-in-aggs.fir

@@ -1,6 +1,6 @@
 ; Check this design makes it through firtool.
 ; RUN: firtool %s --no-dedup
-; RUN: firtool %s --no-dedup --preserve-aggregate=all --scalarize-top-module=false
+; RUN: firtool %s --no-dedup --preserve-aggregate=all --scalarize-public-modules=false
 
 ; Check parsing into open aggregates.
 ; RUN: circt-translate -import-firrtl -verify-diagnostics -split-input-file %s | circt-opt | FileCheck %s

test/firtool/spec/refs/define-flip-to-passive.fir

@@ -1,5 +1,5 @@
 ; RUN: firtool %s
-; RUN: firtool %s -preserve-aggregate=all -scalarize-top-module=false
+; RUN: firtool %s -preserve-aggregate=all -scalarize-public-modules=false
 FIRRTL version 3.0.0
 circuit Foo :
   ; SPEC EXAMPLE BEGIN

test/firtool/spec/refs/define-subelement.fir

@@ -1,5 +1,5 @@
 ; RUN: firtool %s
-; RUN: firtool %s -preserve-aggregate=all -scalarize-top-module=false
+; RUN: firtool %s -preserve-aggregate=all -scalarize-public-modules=false
 FIRRTL version 3.0.0
 circuit Foo:
   ; SPEC EXAMPLE BEGIN

test/firtool/spec/refs/define.fir

@@ -1,5 +1,5 @@
 ; RUN: firtool %s
-; RUN: firtool %s -preserve-aggregate=all -scalarize-top-module=false
+; RUN: firtool %s -preserve-aggregate=all -scalarize-public-modules=false
 FIRRTL version 3.0.0
 circuit Refs:
   ; SPEC EXAMPLE BEGIN

test/firtool/spec/refs/endpoints.fir

@@ -1,5 +1,5 @@
 ; RUN: firtool %s
-; RUN: firtool %s -preserve-aggregate=all -scalarize-top-module=false
+; RUN: firtool %s -preserve-aggregate=all -scalarize-public-modules=false
 FIRRTL version 3.0.0
 circuit Top : %[[
 { "class": "firrtl.transforms.DontTouchAnnotation", "target": "~Top|Top>producer_debug"},

test/firtool/spec/refs/ext.fir

@@ -1,5 +1,5 @@
 ; RUN: firtool %s
-; RUN: firtool %s -preserve-aggregate=all -scalarize-top-module=false
+; RUN: firtool %s -preserve-aggregate=all -scalarize-public-modules=false
 circuit MyExternalModuleWithRefs :
   ; SPEC EXAMPLE BEGIN
   extmodule MyExternalModuleWithRefs :

test/firtool/spec/refs/force_and_release.fir

@@ -1,5 +1,5 @@
 ; RUN: firtool %s
-; RUN: firtool %s -preserve-aggregate=all -scalarize-top-module=false
+; RUN: firtool %s -preserve-aggregate=all -scalarize-public-modules=false
 FIRRTL version 3.0.0
 circuit ForceAndRelease:
   ; SPEC EXAMPLE BEGIN

test/firtool/spec/refs/force_initial.fir

@@ -1,5 +1,5 @@
 ; RUN: firtool %s
-; RUN: firtool %s -preserve-aggregate=all -scalarize-top-module=false
+; RUN: firtool %s -preserve-aggregate=all -scalarize-public-modules=false
 FIRRTL version 3.0.0
 
 circuit ForceAndRelease:

test/firtool/spec/refs/force_nonpassive.fir

@@ -1,5 +1,5 @@
 ; RUN: firtool %s -verify-diagnostics
-; RUN: firtool %s -preserve-aggregate=all -scalarize-top-module=false -verify-diagnostics
+; RUN: firtool %s -preserve-aggregate=all -scalarize-public-modules=false -verify-diagnostics
 FIRRTL version 3.0.0
 
 circuit Top :

test/firtool/spec/refs/forwarding_refs_upwards.fir

@@ -1,5 +1,5 @@
 ; RUN: firtool %s
-; RUN: firtool %s -preserve-aggregate=all -scalarize-top-module=false
+; RUN: firtool %s -preserve-aggregate=all -scalarize-public-modules=false
 circuit Forward:
   ; SPEC EXAMPLE BEGIN
   extmodule Foo : ; XXX: module -> extmodule

test/firtool/spec/refs/forwarding_refs_upwards_narrow.fir

@@ -1,5 +1,5 @@
 ; RUN: firtool %s
-; RUN: firtool %s -preserve-aggregate=all -scalarize-top-module=false
+; RUN: firtool %s -preserve-aggregate=all -scalarize-public-modules=false
 circuit Forward :
   ; SPEC EXAMPLE BEGIN
   extmodule Foo :

test/firtool/spec/refs/in_ref_context.fir

@@ -1,5 +1,5 @@
 ; RUN: firtool %s -verify-diagnostics
-; RUN: firtool %s -preserve-aggregate=all -scalarize-top-module=false -verify-diagnostics
+; RUN: firtool %s -preserve-aggregate=all -scalarize-public-modules=false -verify-diagnostics
 FIRRTL version 3.0.0
 ; expected-error @+27 {{input probes cannot be used}}
 ; expected-note @+19 {{input probe here}}

test/firtool/spec/refs/inference_reset_bad.fir

@@ -1,5 +1,5 @@
 ; RUN: firtool %s -verify-diagnostics
-; RUN: firtool %s -preserve-aggregate=all -scalarize-top-module=false -verify-diagnostics
+; RUN: firtool %s -preserve-aggregate=all -scalarize-public-modules=false -verify-diagnostics
 ; XFAIL: *
 ; https://github.com/llvm/circt/issues/4813
 FIRRTL version 3.0.0

test/firtool/spec/refs/inference_reset_good.fir

@@ -1,5 +1,5 @@
 ; RUN: firtool %s
-; RUN: firtool %s -preserve-aggregate=all -scalarize-top-module=false
+; RUN: firtool %s -preserve-aggregate=all -scalarize-public-modules=false
 FIRRTL version 3.0.0
 circuit ResetInferGood :
   ; SPEC EXAMPLE BEGIN

test/firtool/spec/refs/inference_works.fir

@@ -1,5 +1,5 @@
 ; RUN: firtool %s
-; RUN: firtool %s -preserve-aggregate=all -scalarize-top-module=false
+; RUN: firtool %s -preserve-aggregate=all -scalarize-public-modules=false
 ; NOT SPEC EXAMPLE
 FIRRTL version 3.0.0
 
@@ -16,4 +16,3 @@ circuit MinimumWidth :
     inst u of Uninferred
     connect u.x, x
     connect y, read(u.r)
-

test/firtool/spec/refs/invalid_in.fir

@@ -1,5 +1,5 @@
 ; RUN: firtool %s --verify-diagnostics
-; RUN: firtool %s -preserve-aggregate=all -scalarize-top-module=false --verify-diagnostics
+; RUN: firtool %s -preserve-aggregate=all -scalarize-public-modules=false --verify-diagnostics
 FIRRTL version 3.0.0
 circuit FooUser:
   ; Invalid, per spec

test/firtool/spec/refs/nested_refproducer.fir

@@ -1,5 +1,5 @@
 ; RUN: firtool %s
-; RUN: firtool %s -preserve-aggregate=all -scalarize-top-module=false
+; RUN: firtool %s -preserve-aggregate=all -scalarize-public-modules=false
 FIRRTL version 3.0.0
 circuit RefProducer :
   ; SPEC EXAMPLE BEGIN

test/firtool/spec/refs/nosubaccess.fir

@@ -1,5 +1,5 @@
 ; RUN: firtool %s
-; RUN: firtool %s -preserve-aggregate=all -scalarize-top-module=false
+; RUN: firtool %s -preserve-aggregate=all -scalarize-public-modules=false
 circuit NoSubAccessesWithProbes :
   extmodule Ext :
     output x : {a : Probe<UInt<2>[2]>, b : UInt<2>}[3]

test/firtool/spec/refs/probe_export_simple.fir

@@ -1,5 +1,5 @@
 ; RUN: firtool %s
-; RUN: firtool %s -preserve-aggregate=all -scalarize-top-module=false
+; RUN: firtool %s -preserve-aggregate=all -scalarize-public-modules=false
 circuit MyModule :
   ; SPEC EXAMPLE BEGIN
   module MyModule :
@@ -8,4 +8,3 @@ circuit MyModule :
 
     define r = probe(in)
     ; SPEC EXAMPLE END
-

test/firtool/spec/refs/read.fir

@@ -1,5 +1,5 @@
 ; RUN: firtool %s
-; RUN: firtool %s -preserve-aggregate=all -scalarize-top-module=false
+; RUN: firtool %s -preserve-aggregate=all -scalarize-public-modules=false
 FIRRTL version 3.0.0
 
 circuit Foo :

test/firtool/spec/refs/read_subelement.fir

@@ -1,5 +1,5 @@
 ; RUN: firtool %s
-; RUN: firtool %s -preserve-aggregate=all -scalarize-top-module=false
+; RUN: firtool %s -preserve-aggregate=all -scalarize-public-modules=false
 FIRRTL version 3.0.0
 
 circuit Foo :
@@ -17,4 +17,3 @@ circuit Foo :
     inst f of Foo
     connect x, read(f.p.b) ; indirectly access the probed data
   ; SPEC EXAMPLE END
-

test/firtool/spec/refs/read_subelement_add.fir

@@ -1,5 +1,5 @@
 ; RUN: firtool %s
-; RUN: firtool %s -preserve-aggregate=all -scalarize-top-module=false
+; RUN: firtool %s -preserve-aggregate=all -scalarize-public-modules=false
 FIRRTL version 3.0.0
 
 circuit Foo :