[ImportVerilog] Fix unknown name caused by local variables.

lib/Conversion/ImportVerilog/Statements.cpp

@@ -63,8 +63,11 @@ struct StmtVisitor {
         return failure();
     }
 
-    builder.create<moore::VariableOp>(loc, type,
-                                      builder.getStringAttr(var.name), initial);
+    // Collect local temporary variables.
+    auto varOp = builder.create<moore::VariableOp>(
+        loc, type, builder.getStringAttr(var.name), initial);
+    context.valueSymbols.insertIntoScope(context.valueSymbols.getCurScope(),
+                                         &var, varOp);
     return success();
   }
 

test/Conversion/ImportVerilog/basic.sv

@@ -119,6 +119,12 @@ module Statements;
   bit x, y, z;
   int i;
   initial begin
+    //===------------------------------------------------------------------===//
+    // local variables
+
+    // CHECK: %a = moore.variable  : !moore.int
+    automatic int a;
+
     //===------------------------------------------------------------------===//
     // Conditional statements
 

test/Conversion/ImportVerilog/errors.sv

@@ -163,3 +163,17 @@ module Foo;
     b = a[1-:-1];
   end
 endmodule
+
+// -----
+
+module Foo;
+  int x;
+  initial begin
+    // expected-remark @below {{declared here}}
+    automatic int a;
+    // expected-error @below {{nonblocking assignment to automatic variable 'a' is not allowed}}
+    a <= x;
+    // expected-error @below {{declaration must come before all statements in the block}}
+    automatic int b;
+  end
+endmodule

test/Dialect/Moore/basic.mlir

@@ -58,6 +58,8 @@ moore.module @Foo {
     moore.blocking_assign %v1, %v2 : !moore.bit
     // CHECK: moore.nonblocking_assign %v1, %v2 : !moore.bit
     moore.nonblocking_assign %v1, %v2 : !moore.bit
+    // CHECK: %a = moore.variable  : !moore.int
+    %a = moore.variable  : !moore.int
   }
 }