[RISCV] Enable store clustering by default #73796

asb · 2023-11-29T14:04:51Z

Builds on #73789, enabling store clustering by default using the same heuristic.

asb · 2023-12-06T14:40:36Z

I've force pushed a rebase on top of the latest #77389. The difference vs before is that clustered memory operations are consistently sorted (see here for more details).

github-actions · 2023-12-06T14:41:59Z

✅ With the latest revision this PR passed the C/C++ code formatter.

wangpc-pp · 2024-10-08T09:07:42Z

Reverse ping!
@asb Sorry for bothering, what about store clustering? Can we enable it as well?

After llvm#73789 enabled load clustering, do the same for store clustering.

llvmbot · 2024-10-10T14:29:30Z

@llvm/pr-subscribers-backend-risc-v

@llvm/pr-subscribers-llvm-globalisel

Author: Alex Bradbury (asb)

Changes

Builds on #73789, enabling store clustering by default using the same heuristic. It's not clear if this is desirable, but posting in case anyone has views. As it's stacked on other in-review PRs, you'll want to just look at the most recent commit to see how it impacts the in-tree tests.

Patch is 1.51 MiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/73796.diff

249 Files Affected:

(modified) llvm/lib/Target/RISCV/RISCVTargetMachine.cpp (+2)
(modified) llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll (+21-21)
(modified) llvm/test/CodeGen/RISCV/abds-neg.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/abds.ll (+74-74)
(modified) llvm/test/CodeGen/RISCV/abdu-neg.ll (+4-4)
(modified) llvm/test/CodeGen/RISCV/add-before-shl.ll (+2-2)
(modified) llvm/test/CodeGen/RISCV/alloca.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll (+20-20)
(modified) llvm/test/CodeGen/RISCV/callee-saved-gprs.ll (+56-56)
(modified) llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll (+36-36)
(modified) llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll (+88-88)
(modified) llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll (+2-2)
(modified) llvm/test/CodeGen/RISCV/calling-conv-ilp32e.ll (+256-256)
(modified) llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll (+40-40)
(modified) llvm/test/CodeGen/RISCV/calling-conv-lp64e.ll (+10-10)
(modified) llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll (+5-4)
(modified) llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32e.ll (+11-10)
(modified) llvm/test/CodeGen/RISCV/calling-conv-vector-float.ll (+6-6)
(modified) llvm/test/CodeGen/RISCV/calls.ll (+12-12)
(modified) llvm/test/CodeGen/RISCV/double-calling-conv.ll (+14-14)
(modified) llvm/test/CodeGen/RISCV/double-convert-strict.ll (+2-2)
(modified) llvm/test/CodeGen/RISCV/double-convert.ll (+2-2)
(modified) llvm/test/CodeGen/RISCV/fastcc-bf16.ll (+9-9)
(modified) llvm/test/CodeGen/RISCV/fastcc-float.ll (+9-9)
(modified) llvm/test/CodeGen/RISCV/fastcc-half.ll (+9-9)
(modified) llvm/test/CodeGen/RISCV/fastcc-int.ll (+6-6)
(modified) llvm/test/CodeGen/RISCV/fastcc-without-f-reg.ll (+404-404)
(modified) llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll (+2-2)
(modified) llvm/test/CodeGen/RISCV/forced-atomics.ll (+29-29)
(modified) llvm/test/CodeGen/RISCV/fp128.ll (+34-34)
(modified) llvm/test/CodeGen/RISCV/frame.ll (+6-6)
(modified) llvm/test/CodeGen/RISCV/get-setcc-result-type.ll (+3-3)
(modified) llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll (+2-2)
(modified) llvm/test/CodeGen/RISCV/intrinsic-cttz-elts-vscale.ll (+1-1)
(modified) llvm/test/CodeGen/RISCV/legalize-fneg.ll (+6-6)
(modified) llvm/test/CodeGen/RISCV/llvm.exp10.ll (+27-27)
(modified) llvm/test/CodeGen/RISCV/llvm.frexp.ll (+234-234)
(modified) llvm/test/CodeGen/RISCV/memcpy.ll (+87-87)
(modified) llvm/test/CodeGen/RISCV/memset-inline.ll (+517-517)
(modified) llvm/test/CodeGen/RISCV/neg-abs.ll (+6-4)
(modified) llvm/test/CodeGen/RISCV/nontemporal.ll (+1480-1480)
(modified) llvm/test/CodeGen/RISCV/overflow-intrinsics.ll (+2-2)
(modified) llvm/test/CodeGen/RISCV/pr63816.ll (+6-6)
(modified) llvm/test/CodeGen/RISCV/push-pop-popret.ll (+27-27)
(modified) llvm/test/CodeGen/RISCV/riscv-codegenprepare-asm.ll (+1-1)
(modified) llvm/test/CodeGen/RISCV/riscv-shifted-extend.ll (+4-4)
(modified) llvm/test/CodeGen/RISCV/rv32zbb.ll (+4-4)
(modified) llvm/test/CodeGen/RISCV/rvv/binop-splats.ll (+6-6)
(modified) llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll (+4-4)
(modified) llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll (+10-10)
(modified) llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll (+4-4)
(modified) llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll (+11-11)
(modified) llvm/test/CodeGen/RISCV/rvv/combine-store.ll (+4-4)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-binop-splats.ll (+4-4)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll (+22-22)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll (+2-2)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll (+10-10)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll (+2-2)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll (+3-3)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll (+48-48)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll (+56-83)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll (+48-48)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll (+4-4)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-expandload-int.ll (+4-4)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll (+176-176)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll (+24-24)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll (+6-6)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll (+33-33)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll (+3-3)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll (+2-2)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint.ll (+70-70)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint.ll (+64-64)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll (+260-260)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll (+66-66)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll (+16-16)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll (+18-18)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-vslide1down.ll (+2-2)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-vslide1up.ll (+2-2)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll (+16-16)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-asm.ll (+6-6)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll (+24-24)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vaaddu.ll (+2-2)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll (+10-10)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmacc-vp.ll (+9-9)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnmsac-vp.ll (+9-9)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vp-splat.ll (+4-4)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd-vp.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd.ll (+4-4)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu-vp.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu.ll (+4-4)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub-vp.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll (+4-4)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu-vp.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll (+4-4)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll (+4-4)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwaddu.ll (+7-7)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll (+4-4)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulsu.ll (+3-3)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsub.ll (+4-4)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsubu.ll (+7-7)
(modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll (+180-180)
(modified) llvm/test/CodeGen/RISCV/rvv/masked-tama.ll (+2-2)
(modified) llvm/test/CodeGen/RISCV/rvv/memset-inline.ll (+44-44)
(modified) llvm/test/CodeGen/RISCV/rvv/no-reserved-frame.ll (+4-4)
(modified) llvm/test/CodeGen/RISCV/rvv/pr104480.ll (+2-2)
(modified) llvm/test/CodeGen/RISCV/rvv/rvv-args-by-mem.ll (+1-1)
(modified) llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll (+36-36)
(modified) llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll (+20-20)
(modified) llvm/test/CodeGen/RISCV/rvv/splat-vector-split-i64-vl-sdnode.ll (+1-1)
(modified) llvm/test/CodeGen/RISCV/rvv/stepvector.ll (+17-17)
(modified) llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll (+5-5)
(modified) llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll (+9-9)
(modified) llvm/test/CodeGen/RISCV/rvv/vaadd.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/vaaddu-sdnode.ll (+2-2)
(modified) llvm/test/CodeGen/RISCV/rvv/vaaddu.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/vadc.ll (+4-4)
(modified) llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll (+5-5)
(modified) llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/vadd.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll (+5-5)
(modified) llvm/test/CodeGen/RISCV/rvv/vand-vp.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/vand.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll (+16-16)
(modified) llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/vandn.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/vasub.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/vasubu.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/vclmul.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/vclmulh.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll (+16-16)
(modified) llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/vdiv.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll (+12-12)
(modified) llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/vdivu.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/vec3-setcc-crash.ll (+2-2)
(modified) llvm/test/CodeGen/RISCV/rvv/vmacc-vp.ll (+12-12)
(modified) llvm/test/CodeGen/RISCV/rvv/vmacc.ll (+6-6)
(modified) llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in.ll (+4-4)
(modified) llvm/test/CodeGen/RISCV/rvv/vmadc.ll (+4-4)
(modified) llvm/test/CodeGen/RISCV/rvv/vmadd-sdnode.ll (+4-4)
(modified) llvm/test/CodeGen/RISCV/rvv/vmadd-vp.ll (+12-12)
(modified) llvm/test/CodeGen/RISCV/rvv/vmadd.ll (+6-6)
(modified) llvm/test/CodeGen/RISCV/rvv/vmax-sdnode.ll (+4-4)
(modified) llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/vmax.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode.ll (+4-4)
(modified) llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/vmaxu.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/vmin-sdnode.ll (+4-4)
(modified) llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/vmin.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/vminu-sdnode.ll (+4-4)
(modified) llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/vminu.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in.ll (+4-4)
(modified) llvm/test/CodeGen/RISCV/rvv/vmsbc.ll (+4-4)
(modified) llvm/test/CodeGen/RISCV/rvv/vmseq.ll (+6-6)
(modified) llvm/test/CodeGen/RISCV/rvv/vmsge.ll (+9-9)
(modified) llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll (+9-9)
(modified) llvm/test/CodeGen/RISCV/rvv/vmsgt.ll (+6-6)
(modified) llvm/test/CodeGen/RISCV/rvv/vmsgtu.ll (+6-6)
(modified) llvm/test/CodeGen/RISCV/rvv/vmsle.ll (+6-6)
(modified) llvm/test/CodeGen/RISCV/rvv/vmsleu.ll (+6-6)
(modified) llvm/test/CodeGen/RISCV/rvv/vmslt.ll (+6-6)
(modified) llvm/test/CodeGen/RISCV/rvv/vmsltu.ll (+6-6)
(modified) llvm/test/CodeGen/RISCV/rvv/vmsne.ll (+6-6)
(modified) llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll (+7-7)
(modified) llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/vmul.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/vmulh.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/vmulhsu.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/vmulhu.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/vmv.s.x.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/vmv.v.x.ll (+4-4)
(modified) llvm/test/CodeGen/RISCV/rvv/vnmsac-vp.ll (+12-12)
(modified) llvm/test/CodeGen/RISCV/rvv/vnmsac.ll (+6-6)
(modified) llvm/test/CodeGen/RISCV/rvv/vnmsub-sdnode.ll (+4-4)
(modified) llvm/test/CodeGen/RISCV/rvv/vnmsub.ll (+6-6)
(modified) llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll (+5-5)
(modified) llvm/test/CodeGen/RISCV/rvv/vor-vp.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/vor.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/vp-splat.ll (+4-4)
(modified) llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll (+4-4)
(modified) llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll (+30-30)
(modified) llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll (+16-16)
(modified) llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/vrem.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/vremu-sdnode.ll (+12-12)
(modified) llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/vremu.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode.ll (+4-4)
(modified) llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/vrsub.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll (+4-4)
(modified) llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/vsadd.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/vsaddu-sdnode.ll (+4-4)
(modified) llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/vsaddu.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/vsbc.ll (+4-4)
(modified) llvm/test/CodeGen/RISCV/rvv/vselect-int.ll (+4-4)
(modified) llvm/test/CodeGen/RISCV/rvv/vsmul.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/vssub-sdnode.ll (+4-4)
(modified) llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/vssub.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/vssubu-sdnode.ll (+4-4)
(modified) llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/vssubu.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll (+5-5)
(modified) llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/vsub.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll (+2-2)
(modified) llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll (+5-5)
(modified) llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/rvv/vxor.ll (+8-8)
(modified) llvm/test/CodeGen/RISCV/select-optimize-multiple.ll (+7-7)
(modified) llvm/test/CodeGen/RISCV/shifts.ll (+36-36)
(modified) llvm/test/CodeGen/RISCV/split-offsets.ll (+6-6)
(modified) llvm/test/CodeGen/RISCV/split-store.ll (+2-2)
(modified) llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll (+48-48)
(modified) llvm/test/CodeGen/RISCV/srem-vector-lkk.ll (+115-115)
(modified) llvm/test/CodeGen/RISCV/stack-slot-size.ll (+16-16)
(modified) llvm/test/CodeGen/RISCV/stack-store-check.ll (+243-241)
(modified) llvm/test/CodeGen/RISCV/tail-calls.ll (+16-16)
(modified) llvm/test/CodeGen/RISCV/unaligned-load-store.ll (+70-70)
(modified) llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll (+18-18)
(modified) llvm/test/CodeGen/RISCV/urem-vector-lkk.ll (+108-108)
(modified) llvm/test/CodeGen/RISCV/vararg-ilp32e.ll (+6-6)
(modified) llvm/test/CodeGen/RISCV/vararg.ll (+526-526)
(modified) llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll (+1764-1758)
(modified) llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll (+648-648)
(modified) llvm/test/CodeGen/RISCV/xtheadmempair.ll (+2-2)

diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index 2dcac1320417c2..0d05bd06eba2e4 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -351,6 +351,8 @@ class RISCVPassConfig : public TargetPassConfig {
       DAG = createGenericSchedLive(C);
       DAG->addMutation(createLoadClusterDAGMutation(
           DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
+      DAG->addMutation(createStoreClusterDAGMutation(
+          DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
     }
     return DAG;
   }
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll b/llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
index 3df4aca40ec942..6c0e322a252c72 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
@@ -69,12 +69,12 @@ define i32 @va1(ptr %fmt, ...) {
 ; RV64-NEXT:    sd a2, 32(sp)
 ; RV64-NEXT:    sd a3, 40(sp)
 ; RV64-NEXT:    sd a4, 48(sp)
-; RV64-NEXT:    sd a5, 56(sp)
 ; RV64-NEXT:    addi a0, sp, 8
 ; RV64-NEXT:    addi a1, sp, 24
 ; RV64-NEXT:    sd a1, 8(sp)
 ; RV64-NEXT:    lw a0, 4(a0)
 ; RV64-NEXT:    lwu a1, 8(sp)
+; RV64-NEXT:    sd a5, 56(sp)
 ; RV64-NEXT:    sd a6, 64(sp)
 ; RV64-NEXT:    sd a7, 72(sp)
 ; RV64-NEXT:    slli a0, a0, 32
@@ -129,12 +129,12 @@ define i32 @va1(ptr %fmt, ...) {
 ; RV64-WITHFP-NEXT:    sd a2, 16(s0)
 ; RV64-WITHFP-NEXT:    sd a3, 24(s0)
 ; RV64-WITHFP-NEXT:    sd a4, 32(s0)
-; RV64-WITHFP-NEXT:    sd a5, 40(s0)
 ; RV64-WITHFP-NEXT:    addi a0, s0, -24
 ; RV64-WITHFP-NEXT:    addi a1, s0, 8
 ; RV64-WITHFP-NEXT:    sd a1, -24(s0)
 ; RV64-WITHFP-NEXT:    lw a0, 4(a0)
 ; RV64-WITHFP-NEXT:    lwu a1, -24(s0)
+; RV64-WITHFP-NEXT:    sd a5, 40(s0)
 ; RV64-WITHFP-NEXT:    sd a6, 48(s0)
 ; RV64-WITHFP-NEXT:    sd a7, 56(s0)
 ; RV64-WITHFP-NEXT:    slli a0, a0, 32
@@ -844,11 +844,11 @@ define i64 @va3(i32 %a, i64 %b, ...) nounwind {
 ; ILP32-LABEL: va3:
 ; ILP32:       # %bb.0:
 ; ILP32-NEXT:    addi sp, sp, -32
-; ILP32-NEXT:    sw a3, 12(sp)
-; ILP32-NEXT:    sw a4, 16(sp)
 ; ILP32-NEXT:    addi a0, sp, 12
 ; ILP32-NEXT:    sw a0, 4(sp)
 ; ILP32-NEXT:    lw a0, 4(sp)
+; ILP32-NEXT:    sw a3, 12(sp)
+; ILP32-NEXT:    sw a4, 16(sp)
 ; ILP32-NEXT:    sw a5, 20(sp)
 ; ILP32-NEXT:    sw a6, 24(sp)
 ; ILP32-NEXT:    sw a7, 28(sp)
@@ -868,11 +868,11 @@ define i64 @va3(i32 %a, i64 %b, ...) nounwind {
 ; RV32D-ILP32-LABEL: va3:
 ; RV32D-ILP32:       # %bb.0:
 ; RV32D-ILP32-NEXT:    addi sp, sp, -48
-; RV32D-ILP32-NEXT:    sw a3, 28(sp)
-; RV32D-ILP32-NEXT:    sw a4, 32(sp)
 ; RV32D-ILP32-NEXT:    addi a0, sp, 28
 ; RV32D-ILP32-NEXT:    sw a0, 20(sp)
 ; RV32D-ILP32-NEXT:    lw a0, 20(sp)
+; RV32D-ILP32-NEXT:    sw a3, 28(sp)
+; RV32D-ILP32-NEXT:    sw a4, 32(sp)
 ; RV32D-ILP32-NEXT:    sw a5, 36(sp)
 ; RV32D-ILP32-NEXT:    sw a6, 40(sp)
 ; RV32D-ILP32-NEXT:    sw a7, 44(sp)
@@ -894,11 +894,11 @@ define i64 @va3(i32 %a, i64 %b, ...) nounwind {
 ; RV32D-ILP32F-LABEL: va3:
 ; RV32D-ILP32F:       # %bb.0:
 ; RV32D-ILP32F-NEXT:    addi sp, sp, -48
-; RV32D-ILP32F-NEXT:    sw a3, 28(sp)
-; RV32D-ILP32F-NEXT:    sw a4, 32(sp)
 ; RV32D-ILP32F-NEXT:    addi a0, sp, 28
 ; RV32D-ILP32F-NEXT:    sw a0, 20(sp)
 ; RV32D-ILP32F-NEXT:    lw a0, 20(sp)
+; RV32D-ILP32F-NEXT:    sw a3, 28(sp)
+; RV32D-ILP32F-NEXT:    sw a4, 32(sp)
 ; RV32D-ILP32F-NEXT:    sw a5, 36(sp)
 ; RV32D-ILP32F-NEXT:    sw a6, 40(sp)
 ; RV32D-ILP32F-NEXT:    sw a7, 44(sp)
@@ -920,11 +920,11 @@ define i64 @va3(i32 %a, i64 %b, ...) nounwind {
 ; RV32D-ILP32D-LABEL: va3:
 ; RV32D-ILP32D:       # %bb.0:
 ; RV32D-ILP32D-NEXT:    addi sp, sp, -48
-; RV32D-ILP32D-NEXT:    sw a3, 28(sp)
-; RV32D-ILP32D-NEXT:    sw a4, 32(sp)
 ; RV32D-ILP32D-NEXT:    addi a0, sp, 28
 ; RV32D-ILP32D-NEXT:    sw a0, 20(sp)
 ; RV32D-ILP32D-NEXT:    lw a0, 20(sp)
+; RV32D-ILP32D-NEXT:    sw a3, 28(sp)
+; RV32D-ILP32D-NEXT:    sw a4, 32(sp)
 ; RV32D-ILP32D-NEXT:    sw a5, 36(sp)
 ; RV32D-ILP32D-NEXT:    sw a6, 40(sp)
 ; RV32D-ILP32D-NEXT:    sw a7, 44(sp)
@@ -946,12 +946,12 @@ define i64 @va3(i32 %a, i64 %b, ...) nounwind {
 ; RV64-LABEL: va3:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi sp, sp, -64
-; RV64-NEXT:    sd a2, 16(sp)
-; RV64-NEXT:    sd a3, 24(sp)
-; RV64-NEXT:    sd a4, 32(sp)
 ; RV64-NEXT:    addi a0, sp, 16
 ; RV64-NEXT:    sd a0, 8(sp)
 ; RV64-NEXT:    ld a0, 8(sp)
+; RV64-NEXT:    sd a2, 16(sp)
+; RV64-NEXT:    sd a3, 24(sp)
+; RV64-NEXT:    sd a4, 32(sp)
 ; RV64-NEXT:    sd a5, 40(sp)
 ; RV64-NEXT:    sd a6, 48(sp)
 ; RV64-NEXT:    sd a7, 56(sp)
@@ -970,11 +970,11 @@ define i64 @va3(i32 %a, i64 %b, ...) nounwind {
 ; RV32-WITHFP-NEXT:    sw ra, 20(sp) # 4-byte Folded Spill
 ; RV32-WITHFP-NEXT:    sw s0, 16(sp) # 4-byte Folded Spill
 ; RV32-WITHFP-NEXT:    addi s0, sp, 24
-; RV32-WITHFP-NEXT:    sw a3, 4(s0)
-; RV32-WITHFP-NEXT:    sw a4, 8(s0)
 ; RV32-WITHFP-NEXT:    addi a0, s0, 4
 ; RV32-WITHFP-NEXT:    sw a0, -12(s0)
 ; RV32-WITHFP-NEXT:    lw a0, -12(s0)
+; RV32-WITHFP-NEXT:    sw a3, 4(s0)
+; RV32-WITHFP-NEXT:    sw a4, 8(s0)
 ; RV32-WITHFP-NEXT:    sw a5, 12(s0)
 ; RV32-WITHFP-NEXT:    sw a6, 16(s0)
 ; RV32-WITHFP-NEXT:    sw a7, 20(s0)
@@ -999,12 +999,12 @@ define i64 @va3(i32 %a, i64 %b, ...) nounwind {
 ; RV64-WITHFP-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
 ; RV64-WITHFP-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
 ; RV64-WITHFP-NEXT:    addi s0, sp, 32
-; RV64-WITHFP-NEXT:    sd a2, 0(s0)
-; RV64-WITHFP-NEXT:    sd a3, 8(s0)
-; RV64-WITHFP-NEXT:    sd a4, 16(s0)
 ; RV64-WITHFP-NEXT:    mv a0, s0
 ; RV64-WITHFP-NEXT:    sd a0, -24(s0)
 ; RV64-WITHFP-NEXT:    ld a0, -24(s0)
+; RV64-WITHFP-NEXT:    sd a2, 0(s0)
+; RV64-WITHFP-NEXT:    sd a3, 8(s0)
+; RV64-WITHFP-NEXT:    sd a4, 16(s0)
 ; RV64-WITHFP-NEXT:    sd a5, 24(s0)
 ; RV64-WITHFP-NEXT:    sd a6, 32(s0)
 ; RV64-WITHFP-NEXT:    sd a7, 40(s0)
@@ -1622,9 +1622,6 @@ define i32 @va_large_stack(ptr %fmt, ...) {
 ; RV64-NEXT:    lui a0, 24414
 ; RV64-NEXT:    add a0, sp, a0
 ; RV64-NEXT:    sd a4, 304(a0)
-; RV64-NEXT:    lui a0, 24414
-; RV64-NEXT:    add a0, sp, a0
-; RV64-NEXT:    sd a5, 312(a0)
 ; RV64-NEXT:    addi a0, sp, 8
 ; RV64-NEXT:    lui a1, 24414
 ; RV64-NEXT:    addiw a1, a1, 280
@@ -1634,6 +1631,9 @@ define i32 @va_large_stack(ptr %fmt, ...) {
 ; RV64-NEXT:    lwu a1, 8(sp)
 ; RV64-NEXT:    lui a2, 24414
 ; RV64-NEXT:    add a2, sp, a2
+; RV64-NEXT:    sd a5, 312(a2)
+; RV64-NEXT:    lui a2, 24414
+; RV64-NEXT:    add a2, sp, a2
 ; RV64-NEXT:    sd a6, 320(a2)
 ; RV64-NEXT:    lui a2, 24414
 ; RV64-NEXT:    add a2, sp, a2
diff --git a/llvm/test/CodeGen/RISCV/abds-neg.ll b/llvm/test/CodeGen/RISCV/abds-neg.ll
index b6064198935a61..e7fd87bd783876 100644
--- a/llvm/test/CodeGen/RISCV/abds-neg.ll
+++ b/llvm/test/CodeGen/RISCV/abds-neg.ll
@@ -705,8 +705,8 @@ define i128 @abd_ext_i128(i128 %a, i128 %b) nounwind {
 ; RV32I-NEXT:    sub a4, a4, a3
 ; RV32I-NEXT:    neg a1, a1
 ; RV32I-NEXT:    sw a1, 0(a0)
-; RV32I-NEXT:    sw a4, 8(a0)
 ; RV32I-NEXT:    sw a2, 4(a0)
+; RV32I-NEXT:    sw a4, 8(a0)
 ; RV32I-NEXT:    sw a5, 12(a0)
 ; RV32I-NEXT:    lw s0, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
@@ -824,8 +824,8 @@ define i128 @abd_ext_i128(i128 %a, i128 %b) nounwind {
 ; RV32ZBB-NEXT:    sub a4, a4, a3
 ; RV32ZBB-NEXT:    neg a1, a1
 ; RV32ZBB-NEXT:    sw a1, 0(a0)
-; RV32ZBB-NEXT:    sw a4, 8(a0)
 ; RV32ZBB-NEXT:    sw a2, 4(a0)
+; RV32ZBB-NEXT:    sw a4, 8(a0)
 ; RV32ZBB-NEXT:    sw a5, 12(a0)
 ; RV32ZBB-NEXT:    lw s0, 12(sp) # 4-byte Folded Reload
 ; RV32ZBB-NEXT:    addi sp, sp, 16
@@ -952,8 +952,8 @@ define i128 @abd_ext_i128_undef(i128 %a, i128 %b) nounwind {
 ; RV32I-NEXT:    sub a4, a4, a3
 ; RV32I-NEXT:    neg a1, a1
 ; RV32I-NEXT:    sw a1, 0(a0)
-; RV32I-NEXT:    sw a4, 8(a0)
 ; RV32I-NEXT:    sw a2, 4(a0)
+; RV32I-NEXT:    sw a4, 8(a0)
 ; RV32I-NEXT:    sw a5, 12(a0)
 ; RV32I-NEXT:    lw s0, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
@@ -1071,8 +1071,8 @@ define i128 @abd_ext_i128_undef(i128 %a, i128 %b) nounwind {
 ; RV32ZBB-NEXT:    sub a4, a4, a3
 ; RV32ZBB-NEXT:    neg a1, a1
 ; RV32ZBB-NEXT:    sw a1, 0(a0)
-; RV32ZBB-NEXT:    sw a4, 8(a0)
 ; RV32ZBB-NEXT:    sw a2, 4(a0)
+; RV32ZBB-NEXT:    sw a4, 8(a0)
 ; RV32ZBB-NEXT:    sw a5, 12(a0)
 ; RV32ZBB-NEXT:    lw s0, 12(sp) # 4-byte Folded Reload
 ; RV32ZBB-NEXT:    addi sp, sp, 16
@@ -1918,9 +1918,9 @@ define i128 @abd_cmp_i128(i128 %a, i128 %b) nounwind {
 ; RV32I-NEXT:    sub a1, a1, t2
 ; RV32I-NEXT:    sub a2, a2, a3
 ; RV32I-NEXT:  .LBB22_11:
-; RV32I-NEXT:    sw a6, 8(a0)
-; RV32I-NEXT:    sw a1, 4(a0)
 ; RV32I-NEXT:    sw a2, 0(a0)
+; RV32I-NEXT:    sw a1, 4(a0)
+; RV32I-NEXT:    sw a6, 8(a0)
 ; RV32I-NEXT:    sw a5, 12(a0)
 ; RV32I-NEXT:    ret
 ;
@@ -2005,9 +2005,9 @@ define i128 @abd_cmp_i128(i128 %a, i128 %b) nounwind {
 ; RV32ZBB-NEXT:    sub a1, a1, t2
 ; RV32ZBB-NEXT:    sub a2, a2, a3
 ; RV32ZBB-NEXT:  .LBB22_11:
-; RV32ZBB-NEXT:    sw a6, 8(a0)
-; RV32ZBB-NEXT:    sw a1, 4(a0)
 ; RV32ZBB-NEXT:    sw a2, 0(a0)
+; RV32ZBB-NEXT:    sw a1, 4(a0)
+; RV32ZBB-NEXT:    sw a6, 8(a0)
 ; RV32ZBB-NEXT:    sw a5, 12(a0)
 ; RV32ZBB-NEXT:    ret
 ;
diff --git a/llvm/test/CodeGen/RISCV/abds.ll b/llvm/test/CodeGen/RISCV/abds.ll
index 91b044902a5201..e639d4b30d4c94 100644
--- a/llvm/test/CodeGen/RISCV/abds.ll
+++ b/llvm/test/CodeGen/RISCV/abds.ll
@@ -599,9 +599,9 @@ define i128 @abd_ext_i128(i128 %a, i128 %b) nounwind {
 ; RV32I-NEXT:    sub a1, a4, t5
 ; RV32I-NEXT:    sub a4, a6, t6
 ; RV32I-NEXT:  .LBB11_13:
-; RV32I-NEXT:    sw a4, 8(a0)
-; RV32I-NEXT:    sw a1, 4(a0)
 ; RV32I-NEXT:    sw a3, 0(a0)
+; RV32I-NEXT:    sw a1, 4(a0)
+; RV32I-NEXT:    sw a4, 8(a0)
 ; RV32I-NEXT:    sw a2, 12(a0)
 ; RV32I-NEXT:    lw s0, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
@@ -695,9 +695,9 @@ define i128 @abd_ext_i128(i128 %a, i128 %b) nounwind {
 ; RV32ZBB-NEXT:    sub a1, a4, t5
 ; RV32ZBB-NEXT:    sub a4, a6, t6
 ; RV32ZBB-NEXT:  .LBB11_13:
-; RV32ZBB-NEXT:    sw a4, 8(a0)
-; RV32ZBB-NEXT:    sw a1, 4(a0)
 ; RV32ZBB-NEXT:    sw a3, 0(a0)
+; RV32ZBB-NEXT:    sw a1, 4(a0)
+; RV32ZBB-NEXT:    sw a4, 8(a0)
 ; RV32ZBB-NEXT:    sw a2, 12(a0)
 ; RV32ZBB-NEXT:    lw s0, 12(sp) # 4-byte Folded Reload
 ; RV32ZBB-NEXT:    addi sp, sp, 16
@@ -799,9 +799,9 @@ define i128 @abd_ext_i128_undef(i128 %a, i128 %b) nounwind {
 ; RV32I-NEXT:    sub a1, a4, t5
 ; RV32I-NEXT:    sub a4, a6, t6
 ; RV32I-NEXT:  .LBB12_13:
-; RV32I-NEXT:    sw a4, 8(a0)
-; RV32I-NEXT:    sw a1, 4(a0)
 ; RV32I-NEXT:    sw a3, 0(a0)
+; RV32I-NEXT:    sw a1, 4(a0)
+; RV32I-NEXT:    sw a4, 8(a0)
 ; RV32I-NEXT:    sw a2, 12(a0)
 ; RV32I-NEXT:    lw s0, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
@@ -895,9 +895,9 @@ define i128 @abd_ext_i128_undef(i128 %a, i128 %b) nounwind {
 ; RV32ZBB-NEXT:    sub a1, a4, t5
 ; RV32ZBB-NEXT:    sub a4, a6, t6
 ; RV32ZBB-NEXT:  .LBB12_13:
-; RV32ZBB-NEXT:    sw a4, 8(a0)
-; RV32ZBB-NEXT:    sw a1, 4(a0)
 ; RV32ZBB-NEXT:    sw a3, 0(a0)
+; RV32ZBB-NEXT:    sw a1, 4(a0)
+; RV32ZBB-NEXT:    sw a4, 8(a0)
 ; RV32ZBB-NEXT:    sw a2, 12(a0)
 ; RV32ZBB-NEXT:    lw s0, 12(sp) # 4-byte Folded Reload
 ; RV32ZBB-NEXT:    addi sp, sp, 16
@@ -1188,9 +1188,9 @@ define i128 @abd_minmax_i128(i128 %a, i128 %b) nounwind {
 ; RV32I-NEXT:    sub a1, a4, t5
 ; RV32I-NEXT:    sub a4, a6, t6
 ; RV32I-NEXT:  .LBB17_13:
-; RV32I-NEXT:    sw a4, 8(a0)
-; RV32I-NEXT:    sw a1, 4(a0)
 ; RV32I-NEXT:    sw a3, 0(a0)
+; RV32I-NEXT:    sw a1, 4(a0)
+; RV32I-NEXT:    sw a4, 8(a0)
 ; RV32I-NEXT:    sw a2, 12(a0)
 ; RV32I-NEXT:    lw s0, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
@@ -1284,9 +1284,9 @@ define i128 @abd_minmax_i128(i128 %a, i128 %b) nounwind {
 ; RV32ZBB-NEXT:    sub a1, a4, t5
 ; RV32ZBB-NEXT:    sub a4, a6, t6
 ; RV32ZBB-NEXT:  .LBB17_13:
-; RV32ZBB-NEXT:    sw a4, 8(a0)
-; RV32ZBB-NEXT:    sw a1, 4(a0)
 ; RV32ZBB-NEXT:    sw a3, 0(a0)
+; RV32ZBB-NEXT:    sw a1, 4(a0)
+; RV32ZBB-NEXT:    sw a4, 8(a0)
 ; RV32ZBB-NEXT:    sw a2, 12(a0)
 ; RV32ZBB-NEXT:    lw s0, 12(sp) # 4-byte Folded Reload
 ; RV32ZBB-NEXT:    addi sp, sp, 16
@@ -1579,9 +1579,9 @@ define i128 @abd_cmp_i128(i128 %a, i128 %b) nounwind {
 ; RV32I-NEXT:    sub a1, a4, t5
 ; RV32I-NEXT:    sub a4, a6, t6
 ; RV32I-NEXT:  .LBB22_13:
-; RV32I-NEXT:    sw a4, 8(a0)
-; RV32I-NEXT:    sw a1, 4(a0)
 ; RV32I-NEXT:    sw a3, 0(a0)
+; RV32I-NEXT:    sw a1, 4(a0)
+; RV32I-NEXT:    sw a4, 8(a0)
 ; RV32I-NEXT:    sw a2, 12(a0)
 ; RV32I-NEXT:    lw s0, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
@@ -1675,9 +1675,9 @@ define i128 @abd_cmp_i128(i128 %a, i128 %b) nounwind {
 ; RV32ZBB-NEXT:    sub a1, a4, t5
 ; RV32ZBB-NEXT:    sub a4, a6, t6
 ; RV32ZBB-NEXT:  .LBB22_13:
-; RV32ZBB-NEXT:    sw a4, 8(a0)
-; RV32ZBB-NEXT:    sw a1, 4(a0)
 ; RV32ZBB-NEXT:    sw a3, 0(a0)
+; RV32ZBB-NEXT:    sw a1, 4(a0)
+; RV32ZBB-NEXT:    sw a4, 8(a0)
 ; RV32ZBB-NEXT:    sw a2, 12(a0)
 ; RV32ZBB-NEXT:    lw s0, 12(sp) # 4-byte Folded Reload
 ; RV32ZBB-NEXT:    addi sp, sp, 16
@@ -2043,8 +2043,8 @@ define i64 @abd_subnsw_i64_undef(i64 %a, i64 %b) nounwind {
 define i128 @abd_subnsw_i128(i128 %a, i128 %b) nounwind {
 ; RV32I-LABEL: abd_subnsw_i128:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    lw a3, 0(a2)
-; RV32I-NEXT:    lw a4, 4(a2)
+; RV32I-NEXT:    lw a4, 0(a2)
+; RV32I-NEXT:    lw a3, 4(a2)
 ; RV32I-NEXT:    lw a6, 8(a2)
 ; RV32I-NEXT:    lw t0, 12(a2)
 ; RV32I-NEXT:    lw a2, 8(a1)
@@ -2053,24 +2053,24 @@ define i128 @abd_subnsw_i128(i128 %a, i128 %b) nounwind {
 ; RV32I-NEXT:    lw a7, 4(a1)
 ; RV32I-NEXT:    sltu a1, a2, a6
 ; RV32I-NEXT:    sub t1, t1, t0
-; RV32I-NEXT:    sltu t0, a5, a3
+; RV32I-NEXT:    sltu t0, a5, a4
 ; RV32I-NEXT:    sub a1, t1, a1
 ; RV32I-NEXT:    mv t1, t0
-; RV32I-NEXT:    beq a7, a4, .LBB31_2
+; RV32I-NEXT:    beq a7, a3, .LBB31_2
 ; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    sltu t1, a7, a4
+; RV32I-NEXT:    sltu t1, a7, a3
 ; RV32I-NEXT:  .LBB31_2:
 ; RV32I-NEXT:    sub a2, a2, a6
 ; RV32I-NEXT:    sltu a6, a2, t1
 ; RV32I-NEXT:    sub a1, a1, a6
 ; RV32I-NEXT:    sub a2, a2, t1
-; RV32I-NEXT:    sub a4, a7, a4
-; RV32I-NEXT:    sub a4, a4, t0
-; RV32I-NEXT:    sub a3, a5, a3
+; RV32I-NEXT:    sub a3, a7, a3
+; RV32I-NEXT:    sub a3, a3, t0
+; RV32I-NEXT:    sub a4, a5, a4
 ; RV32I-NEXT:    bgez a1, .LBB31_4
 ; RV32I-NEXT:  # %bb.3:
-; RV32I-NEXT:    snez a5, a4
-; RV32I-NEXT:    snez a6, a3
+; RV32I-NEXT:    snez a5, a3
+; RV32I-NEXT:    snez a6, a4
 ; RV32I-NEXT:    or a5, a6, a5
 ; RV32I-NEXT:    neg a7, a2
 ; RV32I-NEXT:    sltu t0, a7, a5
@@ -2079,12 +2079,12 @@ define i128 @abd_subnsw_i128(i128 %a, i128 %b) nounwind {
 ; RV32I-NEXT:    neg a1, a1
 ; RV32I-NEXT:    sub a1, a1, t0
 ; RV32I-NEXT:    sub a2, a7, a5
-; RV32I-NEXT:    neg a3, a3
-; RV32I-NEXT:    add a4, a4, a6
 ; RV32I-NEXT:    neg a4, a4
+; RV32I-NEXT:    add a3, a3, a6
+; RV32I-NEXT:    neg a3, a3
 ; RV32I-NEXT:  .LBB31_4:
-; RV32I-NEXT:    sw a4, 4(a0)
-; RV32I-NEXT:    sw a3, 0(a0)
+; RV32I-NEXT:    sw a4, 0(a0)
+; RV32I-NEXT:    sw a3, 4(a0)
 ; RV32I-NEXT:    sw a2, 8(a0)
 ; RV32I-NEXT:    sw a1, 12(a0)
 ; RV32I-NEXT:    ret
@@ -2106,8 +2106,8 @@ define i128 @abd_subnsw_i128(i128 %a, i128 %b) nounwind {
 ;
 ; RV32ZBB-LABEL: abd_subnsw_i128:
 ; RV32ZBB:       # %bb.0:
-; RV32ZBB-NEXT:    lw a3, 0(a2)
-; RV32ZBB-NEXT:    lw a4, 4(a2)
+; RV32ZBB-NEXT:    lw a4, 0(a2)
+; RV32ZBB-NEXT:    lw a3, 4(a2)
 ; RV32ZBB-NEXT:    lw a6, 8(a2)
 ; RV32ZBB-NEXT:    lw t0, 12(a2)
 ; RV32ZBB-NEXT:    lw a2, 8(a1)
@@ -2116,24 +2116,24 @@ define i128 @abd_subnsw_i128(i128 %a, i128 %b) nounwind {
 ; RV32ZBB-NEXT:    lw a7, 4(a1)
 ; RV32ZBB-NEXT:    sltu a1, a2, a6
 ; RV32ZBB-NEXT:    sub t1, t1, t0
-; RV32ZBB-NEXT:    sltu t0, a5, a3
+; RV32ZBB-NEXT:    sltu t0, a5, a4
 ; RV32ZBB-NEXT:    sub a1, t1, a1
 ; RV32ZBB-NEXT:    mv t1, t0
-; RV32ZBB-NEXT:    beq a7, a4, .LBB31_2
+; RV32ZBB-NEXT:    beq a7, a3, .LBB31_2
 ; RV32ZBB-NEXT:  # %bb.1:
-; RV32ZBB-NEXT:    sltu t1, a7, a4
+; RV32ZBB-NEXT:    sltu t1, a7, a3
 ; RV32ZBB-NEXT:  .LBB31_2:
 ; RV32ZBB-NEXT:    sub a2, a2, a6
 ; RV32ZBB-NEXT:    sltu a6, a2, t1
 ; RV32ZBB-NEXT:    sub a1, a1, a6
 ; RV32ZBB-NEXT:    sub a2, a2, t1
-; RV32ZBB-NEXT:    sub a4, a7, a4
-; RV32ZBB-NEXT:    sub a4, a4, t0
-; RV32ZBB-NEXT:    sub a3, a5, a3
+; RV32ZBB-NEXT:    sub a3, a7, a3
+; RV32ZBB-NEXT:    sub a3, a3, t0
+; RV32ZBB-NEXT:    sub a4, a5, a4
 ; RV32ZBB-NEXT:    bgez a1, .LBB31_4
 ; RV32ZBB-NEXT:  # %bb.3:
-; RV32ZBB-NEXT:    snez a5, a4
-; RV32ZBB-NEXT:    snez a6, a3
+; RV32ZBB-NEXT:    snez a5, a3
+; RV32ZBB-NEXT:    snez a6, a4
 ; RV32ZBB-NEXT:    or a5, a6, a5
 ; RV32ZBB-NEXT:    neg a7, a2
 ; RV32ZBB-NEXT:    sltu t0, a7, a5
@@ -2142,12 +2142,12 @@ define i128 @abd_subnsw_i128(i128 %a, i128 %b) nounwind {
 ; RV32ZBB-NEXT:    neg a1, a1
 ; RV32ZBB-NEXT:    sub a1, a1, t0
 ; RV32ZBB-NEXT:    sub a2, a7, a5
-; RV32ZBB-NEXT:    neg a3, a3
-; RV32ZBB-NEXT:    add a4, a4, a6
 ; RV32ZBB-NEXT:    neg a4, a4
+; RV32ZBB-NEXT:    add a3, a3, a6
+; RV32ZBB-NEXT:    neg a3, a3
 ; RV32ZBB-NEXT:  .LBB31_4:
-; RV32ZBB-NEXT:    sw a4, 4(a0)
-; RV32ZBB-NEXT:    sw a3, 0(a0)
+; RV32ZBB-NEXT:    sw a4, 0(a0)
+; RV32ZBB-NEXT:    sw a3, 4(a0)
 ; RV32ZBB-NEXT:    sw a2, 8(a0)
 ; RV32ZBB-NEXT:    sw a1, 12(a0)
 ; RV32ZBB-NEXT:    ret
@@ -2174,8 +2174,8 @@ define i128 @abd_subnsw_i128(i128 %a, i128 %b) nounwind {
 define i128 @abd_subnsw_i128_undef(i128 %a, i128 %b) nounwind {
 ; RV32I-LABEL: abd_subnsw_i128_undef:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    lw a3, 0(a2)
-; RV32I-NEXT:    lw a4, 4(a2)
+; RV32I-NEXT:    lw a4, 0(a2)
+; RV32I-NEXT:    lw a3, 4(a2)
 ; RV32I-NEXT:    lw a6, 8(a2)
 ; RV32I-NEXT:    lw t0, 12(a2)
 ; RV32I-NEXT:    lw a2, 8(a1)
@@ -2184,24 +2184,24 @@ define i128 @abd_subnsw_i128_undef(i128 %a, i128 %b) nounwind {
 ; RV32I-NEXT:    lw a7, 4(a1)
 ; RV32I-NEXT:    sltu a1, a2, a6
 ; RV32I-NEXT:    sub t1, t1, t0
-; RV32I-NEXT:    sltu t0, a5, a3
+; RV32I-NEXT:    sltu t0, a5, a4
 ; RV32I-NEXT:    sub a1, t1, a1
 ; RV32I-NEXT:    mv t1, t0
-; RV32I-NEXT:    beq a7, a4, .LBB32_2
+; RV32I-NEXT:    beq a7, a3, .LBB32_2
 ; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    sltu t1, a7, a4
+; RV32I-NEXT:    sltu t1, a7, a3
 ; RV32I-NEXT:  .LBB32_2:
 ; RV32I-NEXT:    sub a2, a2, a6
 ; RV32I-NEXT:    sltu a6, a2, t1
 ; RV32I-NEXT:    sub a1, a1, a6
 ; RV32I-NEXT:    sub a2, a2, t1
-; RV32I-NEXT:    sub a4, a7, a4
-; RV32I-NEXT:    sub a4, a4, t0
-; RV32I-NEXT:    sub a3, a5, a3
+; RV32I-NEXT:    sub a3, a7, a3
+; RV32I-NEXT:    sub a3, a3, t0
+; RV32I-NEXT:    sub a4, a5, a4
 ; RV32I-NEXT:    bgez a1, .LBB32_4
 ; RV32I-NEXT:  # %bb.3:
-; RV32I-NEXT:    snez a5, a4
-; RV32I-NEXT:    snez a6, a3
+; RV32I-NEXT:    snez a5, a3
+; RV32I-NEXT:    snez a6, a4
 ; RV32I-NEXT:    or a5, a6, a5
 ; RV32I-NEXT:    neg a7, a2
 ; RV32I-NEXT:    sltu t0, a7, a5
@@ -2210,12 +2210,12 @@ define i128 @abd_subnsw_i128_undef(i128 %a, i128 %b) nounwind {
 ; RV32I-NEXT:    neg a1, a1
 ; RV32I-NEXT:    sub a1, a1, t0
 ; RV32I-NEXT:    sub a2, a7, a5
-; RV32I-NEXT:    neg a3, a3
-; RV32I-NEXT:    add a4, a4, a6
 ; RV32I-NEXT:    neg a4, a4
+; RV32I-NEXT:    add a3, a3, a6
+; RV32I-NEXT:    neg a3, a3
 ; RV32I-NEXT:  .LBB32_4:
-; RV32I-NEXT:    sw a4, 4(a0)
-; RV32I-NEXT:    sw a3, 0(a0)
+; RV32I-NEXT:    sw a4, 0(a0)
+; RV32I-NEXT:    sw a3, 4(a0)
 ; RV32I-NEXT:    sw a2, 8(a0)
 ; RV32I-NEXT:    sw a1, 12(a0)
 ; RV32I-NEXT:    ret
@@ -2237,8 +2237,8 @@ define i128 @abd_subnsw_i128_undef(i128 %a, i128 %b) nounwind {
 ;
 ; RV32ZBB-LABEL: abd_subnsw_i128_undef:
 ; RV32ZBB:       # %bb.0:
-; RV32ZBB-NEXT:    lw a3, 0(a2)
-; RV32ZBB-NEXT:    lw a4, 4(a2)
+; RV32ZBB-NEXT:    lw a4, 0(a2)
+; RV32ZBB-NEXT:    lw a3, 4(a2)
 ; RV32ZBB-NEXT:    lw a6, 8(a2)
 ; RV32ZBB-NEXT:    lw t0, 12(a2)
 ; RV32ZBB-NEXT:    lw a2, 8(a1)
@@ -2247,24 +2247,24 @@ define i128 @abd_subnsw_i128_undef(i128 %a, i128 %b) nounwind {
 ; RV32ZBB-NEXT:    lw a7, 4(a1)
 ; RV32ZBB-NEXT:    sltu a1, a2, a6
 ; RV32ZBB-NEXT:    sub t1, t1, t0
-; RV32ZBB-NEXT:    sltu t0, a5, a3
+; RV32ZBB-NEXT:    sltu t0, a5, a4
 ; RV32ZBB-NEXT:    sub a1, t1, a1
 ; RV32ZBB-NEXT:    mv t1, t0
-; RV32ZBB-NEXT:    beq a7, a4, .LBB32_2
+; RV32ZBB-NEXT:    beq a7, a3, .LBB32_2
 ; RV32ZBB-NEXT:  # %bb.1:
-; RV32ZBB-NEXT:    sltu t1, a7, a4
+; RV32ZBB-NEXT:    sltu t1, a7, a3
 ; RV32ZBB-NEXT:  .LBB32_2:
 ; RV32ZBB-NEXT:    sub a2, a2, a6
 ; RV32ZBB-NEXT:    sltu a6, a2, t1
 ; RV32ZBB-NEXT:    sub a1, a1, a6
 ; RV32ZBB-NEXT:    sub a2, a2, t1
-; RV32ZBB-NEXT:    sub a4, a7, a4
-; RV32ZBB-...
[truncated]

asb · 2024-10-10T14:35:05Z

Reverse ping! @asb Sorry for bothering, what about store clustering? Can we enable it as well?

Thanks for the ping - I've gone ahead and rebased this, and also gone back and dug out my old notes on this. I think this should be find to go ahead with on the same basis as the previous load clustering patch. And this then matches AArch64. I would like to better understand the comments in #111504 - I'll follow up there. Though if it's "just" a further tweak on top of this, the best path is probably to land this then review the other patch. (EDIT: more closely looking at the other patch, and after the discussion in the sync-up call I think it's definitely not a blocker on this PR.)

wangpc-pp

LGTM. Thanks!

preames

LGTM

I have skimmed (most of) the tests, and see nothing concerning.

I do see a couple possibilities for store merging, but that's an entirely different topic. For later consideration, the two interesting sub-cases I noticed are: both are storing zero, and we have zbkb.

llvm-ci · 2024-10-11T19:36:12Z

LLVM Buildbot has detected a new failure on builder ml-opt-rel-x86-64 running on ml-opt-rel-x86-64-b1 while building llvm at step 6 "test-build-unified-tree-check-all".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/185/builds/6740

Here is the relevant piece of the build log for the reference

Step 6 (test-build-unified-tree-check-all) failure: test (failure)
******************** TEST 'LLVM :: CodeGen/RISCV/orc-b-patterns.ll' FAILED ********************
Exit Code: 1

Command Output (stderr):
--
RUN: at line 2: /b/ml-opt-rel-x86-64-b1/build/bin/llc -mtriple=riscv32 -verify-machineinstrs < /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/test/CodeGen/RISCV/orc-b-patterns.ll    | /b/ml-opt-rel-x86-64-b1/build/bin/FileCheck /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/test/CodeGen/RISCV/orc-b-patterns.ll -check-prefixes=CHECK,RV32I
+ /b/ml-opt-rel-x86-64-b1/build/bin/FileCheck /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/test/CodeGen/RISCV/orc-b-patterns.ll -check-prefixes=CHECK,RV32I
+ /b/ml-opt-rel-x86-64-b1/build/bin/llc -mtriple=riscv32 -verify-machineinstrs
/b/ml-opt-rel-x86-64-b1/llvm-project/llvm/test/CodeGen/RISCV/orc-b-patterns.ll:342:15: error: CHECK-NEXT: is not on the line after the previous match
; CHECK-NEXT: sw a2, 0(a1)
              ^
<stdin>:253:2: note: 'next' match was here
 sw a2, 0(a1)
 ^
<stdin>:251:16: note: previous match ended here
 srli a3, a0, 1
               ^
<stdin>:252:1: note: non-matching line after previous match is here
 sub a0, a2, a3
^

Input file: <stdin>
Check file: /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/test/CodeGen/RISCV/orc-b-patterns.ll

-dump-input=help explains the following input dump.

Input was:
<<<<<<
          .
          .
          .
        248:  addi a2, a2, 514 
        249:  and a0, a0, a2 
        250:  slli a2, a0, 7 
        251:  srli a3, a0, 1 
        252:  sub a0, a2, a3 
        253:  sw a2, 0(a1) 
next:342      !~~~~~~~~~~~  error: match on wrong line
        254:  sw a3, 4(a1) 
        255:  ret 
        256: .Lfunc_end14: 
        257:  .size orc_b_i32_sub_shl8x_x_b1_both_used, .Lfunc_end14-orc_b_i32_sub_shl8x_x_b1_both_used 
        258:  .cfi_endproc 
          .
          .
          .
>>>>>>

--

...

llvm-ci · 2024-10-11T19:37:02Z

LLVM Buildbot has detected a new failure on builder ml-opt-devrel-x86-64 running on ml-opt-devrel-x86-64-b2 while building llvm at step 6 "test-build-unified-tree-check-all".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/175/builds/6756

Here is the relevant piece of the build log for the reference

Step 6 (test-build-unified-tree-check-all) failure: test (failure)
******************** TEST 'LLVM :: CodeGen/RISCV/orc-b-patterns.ll' FAILED ********************
Exit Code: 1

Command Output (stderr):
--
RUN: at line 2: /b/ml-opt-devrel-x86-64-b1/build/bin/llc -mtriple=riscv32 -verify-machineinstrs < /b/ml-opt-devrel-x86-64-b1/llvm-project/llvm/test/CodeGen/RISCV/orc-b-patterns.ll    | /b/ml-opt-devrel-x86-64-b1/build/bin/FileCheck /b/ml-opt-devrel-x86-64-b1/llvm-project/llvm/test/CodeGen/RISCV/orc-b-patterns.ll -check-prefixes=CHECK,RV32I
+ /b/ml-opt-devrel-x86-64-b1/build/bin/FileCheck /b/ml-opt-devrel-x86-64-b1/llvm-project/llvm/test/CodeGen/RISCV/orc-b-patterns.ll -check-prefixes=CHECK,RV32I
+ /b/ml-opt-devrel-x86-64-b1/build/bin/llc -mtriple=riscv32 -verify-machineinstrs
/b/ml-opt-devrel-x86-64-b1/llvm-project/llvm/test/CodeGen/RISCV/orc-b-patterns.ll:342:15: error: CHECK-NEXT: is not on the line after the previous match
; CHECK-NEXT: sw a2, 0(a1)
              ^
<stdin>:253:2: note: 'next' match was here
 sw a2, 0(a1)
 ^
<stdin>:251:16: note: previous match ended here
 srli a3, a0, 1
               ^
<stdin>:252:1: note: non-matching line after previous match is here
 sub a0, a2, a3
^

Input file: <stdin>
Check file: /b/ml-opt-devrel-x86-64-b1/llvm-project/llvm/test/CodeGen/RISCV/orc-b-patterns.ll

-dump-input=help explains the following input dump.

Input was:
<<<<<<
          .
          .
          .
        248:  addi a2, a2, 514 
        249:  and a0, a0, a2 
        250:  slli a2, a0, 7 
        251:  srli a3, a0, 1 
        252:  sub a0, a2, a3 
        253:  sw a2, 0(a1) 
next:342      !~~~~~~~~~~~  error: match on wrong line
        254:  sw a3, 4(a1) 
        255:  ret 
        256: .Lfunc_end14: 
        257:  .size orc_b_i32_sub_shl8x_x_b1_both_used, .Lfunc_end14-orc_b_i32_sub_shl8x_x_b1_both_used 
        258:  .cfi_endproc 
          .
          .
          .
>>>>>>

--

...

llvm-ci · 2024-10-11T20:30:10Z

LLVM Buildbot has detected a new failure on builder lld-x86_64-ubuntu-fast running on as-builder-4 while building llvm at step 6 "test-build-unified-tree-check-all".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/33/builds/4648

Here is the relevant piece of the build log for the reference

Step 6 (test-build-unified-tree-check-all) failure: test (failure)
******************** TEST 'LLVM :: CodeGen/RISCV/orc-b-patterns.ll' FAILED ********************
Exit Code: 1

Command Output (stderr):
--
RUN: at line 2: /home/buildbot/worker/as-builder-4/ramdisk/lld-x86_64/build/bin/llc -mtriple=riscv32 -verify-machineinstrs < /home/buildbot/worker/as-builder-4/ramdisk/lld-x86_64/llvm-project/llvm/test/CodeGen/RISCV/orc-b-patterns.ll    | /home/buildbot/worker/as-builder-4/ramdisk/lld-x86_64/build/bin/FileCheck /home/buildbot/worker/as-builder-4/ramdisk/lld-x86_64/llvm-project/llvm/test/CodeGen/RISCV/orc-b-patterns.ll -check-prefixes=CHECK,RV32I
+ /home/buildbot/worker/as-builder-4/ramdisk/lld-x86_64/build/bin/llc -mtriple=riscv32 -verify-machineinstrs
+ /home/buildbot/worker/as-builder-4/ramdisk/lld-x86_64/build/bin/FileCheck /home/buildbot/worker/as-builder-4/ramdisk/lld-x86_64/llvm-project/llvm/test/CodeGen/RISCV/orc-b-patterns.ll -check-prefixes=CHECK,RV32I
/home/buildbot/worker/as-builder-4/ramdisk/lld-x86_64/llvm-project/llvm/test/CodeGen/RISCV/orc-b-patterns.ll:342:15: error: CHECK-NEXT: is not on the line after the previous match
; CHECK-NEXT: sw a2, 0(a1)
              ^
<stdin>:253:2: note: 'next' match was here
 sw a2, 0(a1)
 ^
<stdin>:251:16: note: previous match ended here
 srli a3, a0, 1
               ^
<stdin>:252:1: note: non-matching line after previous match is here
 sub a0, a2, a3
^

Input file: <stdin>
Check file: /home/buildbot/worker/as-builder-4/ramdisk/lld-x86_64/llvm-project/llvm/test/CodeGen/RISCV/orc-b-patterns.ll

-dump-input=help explains the following input dump.

Input was:
<<<<<<
          .
          .
          .
        248:  addi a2, a2, 514 
        249:  and a0, a0, a2 
        250:  slli a2, a0, 7 
        251:  srli a3, a0, 1 
        252:  sub a0, a2, a3 
        253:  sw a2, 0(a1) 
next:342      !~~~~~~~~~~~  error: match on wrong line
        254:  sw a3, 4(a1) 
        255:  ret 
        256: .Lfunc_end14: 
        257:  .size orc_b_i32_sub_shl8x_x_b1_both_used, .Lfunc_end14-orc_b_i32_sub_shl8x_x_b1_both_used 
        258:  .cfi_endproc 
          .
          .
          .
>>>>>>

--

...

topperc · 2024-10-11T21:29:59Z

@asb I pushed 8b46d40 to fix the failures

llvm-ci · 2024-10-11T22:55:51Z

LLVM Buildbot has detected a new failure on builder premerge-monolithic-linux running on premerge-linux-1 while building llvm at step 7 "test-build-unified-tree-check-all".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/153/builds/11638

Here is the relevant piece of the build log for the reference

Step 7 (test-build-unified-tree-check-all) failure: test (failure)
******************** TEST 'LLVM :: CodeGen/RISCV/orc-b-patterns.ll' FAILED ********************
Exit Code: 1

Command Output (stderr):
--
RUN: at line 2: /build/buildbot/premerge-monolithic-linux/build/bin/llc -mtriple=riscv32 -verify-machineinstrs < /build/buildbot/premerge-monolithic-linux/llvm-project/llvm/test/CodeGen/RISCV/orc-b-patterns.ll    | /build/buildbot/premerge-monolithic-linux/build/bin/FileCheck /build/buildbot/premerge-monolithic-linux/llvm-project/llvm/test/CodeGen/RISCV/orc-b-patterns.ll -check-prefixes=CHECK,RV32I
+ /build/buildbot/premerge-monolithic-linux/build/bin/llc -mtriple=riscv32 -verify-machineinstrs
+ /build/buildbot/premerge-monolithic-linux/build/bin/FileCheck /build/buildbot/premerge-monolithic-linux/llvm-project/llvm/test/CodeGen/RISCV/orc-b-patterns.ll -check-prefixes=CHECK,RV32I
/build/buildbot/premerge-monolithic-linux/llvm-project/llvm/test/CodeGen/RISCV/orc-b-patterns.ll:342:15: error: CHECK-NEXT: is not on the line after the previous match
; CHECK-NEXT: sw a2, 0(a1)
              ^
<stdin>:253:2: note: 'next' match was here
 sw a2, 0(a1)
 ^
<stdin>:251:16: note: previous match ended here
 srli a3, a0, 1
               ^
<stdin>:252:1: note: non-matching line after previous match is here
 sub a0, a2, a3
^

Input file: <stdin>
Check file: /build/buildbot/premerge-monolithic-linux/llvm-project/llvm/test/CodeGen/RISCV/orc-b-patterns.ll

-dump-input=help explains the following input dump.

Input was:
<<<<<<
          .
          .
          .
        248:  addi a2, a2, 514 
        249:  and a0, a0, a2 
        250:  slli a2, a0, 7 
        251:  srli a3, a0, 1 
        252:  sub a0, a2, a3 
        253:  sw a2, 0(a1) 
next:342      !~~~~~~~~~~~  error: match on wrong line
        254:  sw a3, 4(a1) 
        255:  ret 
        256: .Lfunc_end14: 
        257:  .size orc_b_i32_sub_shl8x_x_b1_both_used, .Lfunc_end14-orc_b_i32_sub_shl8x_x_b1_both_used 
        258:  .cfi_endproc 
          .
          .
          .
>>>>>>

--

...

asb · 2024-10-12T06:41:14Z

@asb I pushed 8b46d40 to fix the failures

Thank you! My bad for not anticipating there had likely been new tests added.

llvm-ci · 2024-10-12T09:12:47Z

LLVM Buildbot has detected a new failure on builder llvm-clang-x86_64-expensive-checks-debian running on gribozavr4 while building llvm at step 6 "test-build-unified-tree-check-all".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/16/builds/7023

Here is the relevant piece of the build log for the reference

Step 6 (test-build-unified-tree-check-all) failure: test (failure)
******************** TEST 'LLVM :: CodeGen/RISCV/orc-b-patterns.ll' FAILED ********************
Exit Code: 1

Command Output (stderr):
--
RUN: at line 2: /b/1/llvm-clang-x86_64-expensive-checks-debian/build/bin/llc -mtriple=riscv32 -verify-machineinstrs < /b/1/llvm-clang-x86_64-expensive-checks-debian/llvm-project/llvm/test/CodeGen/RISCV/orc-b-patterns.ll    | /b/1/llvm-clang-x86_64-expensive-checks-debian/build/bin/FileCheck /b/1/llvm-clang-x86_64-expensive-checks-debian/llvm-project/llvm/test/CodeGen/RISCV/orc-b-patterns.ll -check-prefixes=CHECK,RV32I
+ /b/1/llvm-clang-x86_64-expensive-checks-debian/build/bin/FileCheck /b/1/llvm-clang-x86_64-expensive-checks-debian/llvm-project/llvm/test/CodeGen/RISCV/orc-b-patterns.ll -check-prefixes=CHECK,RV32I
+ /b/1/llvm-clang-x86_64-expensive-checks-debian/build/bin/llc -mtriple=riscv32 -verify-machineinstrs
/b/1/llvm-clang-x86_64-expensive-checks-debian/llvm-project/llvm/test/CodeGen/RISCV/orc-b-patterns.ll:342:15: error: CHECK-NEXT: is not on the line after the previous match
; CHECK-NEXT: sw a2, 0(a1)
              ^
<stdin>:253:2: note: 'next' match was here
 sw a2, 0(a1)
 ^
<stdin>:251:16: note: previous match ended here
 srli a3, a0, 1
               ^
<stdin>:252:1: note: non-matching line after previous match is here
 sub a0, a2, a3
^

Input file: <stdin>
Check file: /b/1/llvm-clang-x86_64-expensive-checks-debian/llvm-project/llvm/test/CodeGen/RISCV/orc-b-patterns.ll

-dump-input=help explains the following input dump.

Input was:
<<<<<<
          .
          .
          .
        248:  addi a2, a2, 514 
        249:  and a0, a0, a2 
        250:  slli a2, a0, 7 
        251:  srli a3, a0, 1 
        252:  sub a0, a2, a3 
        253:  sw a2, 0(a1) 
next:342      !~~~~~~~~~~~  error: match on wrong line
        254:  sw a3, 4(a1) 
        255:  ret 
        256: .Lfunc_end14: 
        257:  .size orc_b_i32_sub_shl8x_x_b1_both_used, .Lfunc_end14-orc_b_i32_sub_shl8x_x_b1_both_used 
        258:  .cfi_endproc 
          .
          .
          .
>>>>>>

--

...

llvm-ci · 2024-10-12T09:19:02Z

LLVM Buildbot has detected a new failure on builder clang-x86_64-debian-fast running on gribozavr4 while building llvm at step 6 "test-build-unified-tree-check-all".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/56/builds/9706

Here is the relevant piece of the build log for the reference

Step 6 (test-build-unified-tree-check-all) failure: test (failure)
******************** TEST 'LLVM :: CodeGen/RISCV/orc-b-patterns.ll' FAILED ********************
Exit Code: 1

Command Output (stderr):
--
RUN: at line 2: /b/1/clang-x86_64-debian-fast/llvm.obj/bin/llc -mtriple=riscv32 -verify-machineinstrs < /b/1/clang-x86_64-debian-fast/llvm.src/llvm/test/CodeGen/RISCV/orc-b-patterns.ll    | /b/1/clang-x86_64-debian-fast/llvm.obj/bin/FileCheck /b/1/clang-x86_64-debian-fast/llvm.src/llvm/test/CodeGen/RISCV/orc-b-patterns.ll -check-prefixes=CHECK,RV32I
+ /b/1/clang-x86_64-debian-fast/llvm.obj/bin/llc -mtriple=riscv32 -verify-machineinstrs
+ /b/1/clang-x86_64-debian-fast/llvm.obj/bin/FileCheck /b/1/clang-x86_64-debian-fast/llvm.src/llvm/test/CodeGen/RISCV/orc-b-patterns.ll -check-prefixes=CHECK,RV32I
/b/1/clang-x86_64-debian-fast/llvm.src/llvm/test/CodeGen/RISCV/orc-b-patterns.ll:342:15: error: CHECK-NEXT: is not on the line after the previous match
; CHECK-NEXT: sw a2, 0(a1)
              ^
<stdin>:253:2: note: 'next' match was here
 sw a2, 0(a1)
 ^
<stdin>:251:16: note: previous match ended here
 srli a3, a0, 1
               ^
<stdin>:252:1: note: non-matching line after previous match is here
 sub a0, a2, a3
^

Input file: <stdin>
Check file: /b/1/clang-x86_64-debian-fast/llvm.src/llvm/test/CodeGen/RISCV/orc-b-patterns.ll

-dump-input=help explains the following input dump.

Input was:
<<<<<<
          .
          .
          .
        248:  addi a2, a2, 514 
        249:  and a0, a0, a2 
        250:  slli a2, a0, 7 
        251:  srli a3, a0, 1 
        252:  sub a0, a2, a3 
        253:  sw a2, 0(a1) 
next:342      !~~~~~~~~~~~  error: match on wrong line
        254:  sw a3, 4(a1) 
        255:  ret 
        256: .Lfunc_end14: 
        257:  .size orc_b_i32_sub_shl8x_x_b1_both_used, .Lfunc_end14-orc_b_i32_sub_shl8x_x_b1_both_used 
        258:  .cfi_endproc 
          .
          .
          .
>>>>>>

--

...

llvm-ci · 2024-10-12T09:20:11Z

LLVM Buildbot has detected a new failure on builder llvm-x86_64-debian-dylib running on gribozavr4 while building llvm at step 7 "test-build-unified-tree-check-llvm".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/60/builds/10067

Here is the relevant piece of the build log for the reference

Step 7 (test-build-unified-tree-check-llvm) failure: test (failure)
******************** TEST 'LLVM :: CodeGen/RISCV/orc-b-patterns.ll' FAILED ********************
Exit Code: 1

Command Output (stderr):
--
RUN: at line 2: /b/1/llvm-x86_64-debian-dylib/build/bin/llc -mtriple=riscv32 -verify-machineinstrs < /b/1/llvm-x86_64-debian-dylib/llvm-project/llvm/test/CodeGen/RISCV/orc-b-patterns.ll    | /b/1/llvm-x86_64-debian-dylib/build/bin/FileCheck /b/1/llvm-x86_64-debian-dylib/llvm-project/llvm/test/CodeGen/RISCV/orc-b-patterns.ll -check-prefixes=CHECK,RV32I
+ /b/1/llvm-x86_64-debian-dylib/build/bin/llc -mtriple=riscv32 -verify-machineinstrs
+ /b/1/llvm-x86_64-debian-dylib/build/bin/FileCheck /b/1/llvm-x86_64-debian-dylib/llvm-project/llvm/test/CodeGen/RISCV/orc-b-patterns.ll -check-prefixes=CHECK,RV32I
/b/1/llvm-x86_64-debian-dylib/llvm-project/llvm/test/CodeGen/RISCV/orc-b-patterns.ll:342:15: error: CHECK-NEXT: is not on the line after the previous match
; CHECK-NEXT: sw a2, 0(a1)
              ^
<stdin>:253:2: note: 'next' match was here
 sw a2, 0(a1)
 ^
<stdin>:251:16: note: previous match ended here
 srli a3, a0, 1
               ^
<stdin>:252:1: note: non-matching line after previous match is here
 sub a0, a2, a3
^

Input file: <stdin>
Check file: /b/1/llvm-x86_64-debian-dylib/llvm-project/llvm/test/CodeGen/RISCV/orc-b-patterns.ll

-dump-input=help explains the following input dump.

Input was:
<<<<<<
          .
          .
          .
        248:  addi a2, a2, 514 
        249:  and a0, a0, a2 
        250:  slli a2, a0, 7 
        251:  srli a3, a0, 1 
        252:  sub a0, a2, a3 
        253:  sw a2, 0(a1) 
next:342      !~~~~~~~~~~~  error: match on wrong line
        254:  sw a3, 4(a1) 
        255:  ret 
        256: .Lfunc_end14: 
        257:  .size orc_b_i32_sub_shl8x_x_b1_both_used, .Lfunc_end14-orc_b_i32_sub_shl8x_x_b1_both_used 
        258:  .cfi_endproc 
          .
          .
          .
>>>>>>

--

...

Builds on llvm#73789, enabling store clustering by default using the same heuristic.

#73789 added load clustering and #73796 tried to add store clustering. If post machine schedule is used, previous cluster of load/store which formed in machine schedule may break. In order to solve this, add load/sotre clustering to post machine schedule.

asb requested review from preames, kito-cheng, topperc and wangpc-pp November 29, 2023 14:04

asb force-pushed the 2023q4-riscv-cluster-memops-3 branch from e2742f4 to e5eaf0c Compare December 6, 2023 14:39

asb mentioned this pull request Dec 6, 2023

[RISCV][RFC/WIP] Enable load clustering in SelectionDAG scheduler #74600

Draft

dtcxzyw mentioned this pull request Mar 8, 2024

[Question] No RISC-V Store clustering #84449

Open

BoyaoWang430 mentioned this pull request Oct 8, 2024

[RISCV] Add load/store clustering in post machine schedule #111504

Merged

wangpc-pp requested review from michaelmaitland and dtcxzyw October 8, 2024 09:08

[RISCV] Enable store clustering by default

2832ed3

After llvm#73789 enabled load clustering, do the same for store clustering.

asb force-pushed the 2023q4-riscv-cluster-memops-3 branch from e5eaf0c to 2832ed3 Compare October 10, 2024 14:28

asb marked this pull request as ready for review October 10, 2024 14:28

llvmbot added backend:RISC-V llvm:globalisel labels Oct 10, 2024

asb changed the title ~~[RISCV][RFC] Enable store clustering by default~~ [RISCV] Enable store clustering by default Oct 10, 2024

Rename option to riscv-misched-load-store-clustering

03d2a2a

wangpc-pp approved these changes Oct 10, 2024

View reviewed changes

preames approved these changes Oct 10, 2024

View reviewed changes

asb merged commit 2967e5f into llvm:main Oct 11, 2024
8 checks passed

DanielCChen pushed a commit to DanielCChen/llvm-project that referenced this pull request Oct 16, 2024

[RISCV] Enable store clustering by default (llvm#73796)

585babe

Builds on llvm#73789, enabling store clustering by default using the same heuristic.

bricknerb pushed a commit to bricknerb/llvm-project that referenced this pull request Oct 17, 2024

[RISCV] Enable store clustering by default (llvm#73796)

985e934

Builds on llvm#73789, enabling store clustering by default using the same heuristic.

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[RISCV] Enable store clustering by default #73796

[RISCV] Enable store clustering by default #73796

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[RISCV] Enable store clustering by default #73796

[RISCV] Enable store clustering by default #73796

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