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This Month in PLCT: Issue 47 (July 1, 2023)

Preface

RISC-V's outreach has been moving forward at blinding pace in the past month. In June, we saw the opening of the inaugural RISC-V Summit in Europe, RISC-V Day in Tokyo, the return of SiFive's tour in mainland China, as well as the Chinese Academy of Sciences' first RuyiSDK Open Day. We would also like to take this moment to congratulate Dr. Qiu Ji 邱吉 at the PLCT Lab for becoming a RISC-V Ambassador at RISC-V International.

Still, we are reminded of RISC-V founder Dr. Krste's comment that software ecosystem is of utmost importance of rhte success of an instruction set architecture. We must realise that, despite the unstoppable forward movement of open source software success, commercial and industrial software support for RISC-V still leaves much room for further development. To realise this development, we will congregate more talents and resources. In the next three to five years, we plan to port and optimize top-1000 software solutions from 18 foundational and key industries. Let's work together and make it happen.

For those who joined PLCT for over a year, June marked a moment for farewell. From late June, the PLCT Lab will encourage and instruct young engineers to find new venues for further self-development. The organizational adjustment will affect about half of our employees, lasting into Q3 2023. While there may be pain and sadness, this adjustment also marks for many a ticket into a promising new future.

Featured Items

V8 for RISC-V

OpenJDK Upstreaming (RV64)

OpenJDK Upstreaming (Zhang Dingli [张定立])

OpenJDK Upstreaming (Cao Gui [曹贵])

  • Submitted and merged JDK-mainline patches.
    • openjdk/jdk#14279 | 8309332: RISC-V: Improve PrintOptoAssembly output of vector nodes
    • openjdk/jdk#14308 | 8309419: RISC-V: Relax register constraint for AddReductionVF & AddReductionVD nodes
    • openjdk/jdk#14510 | 8310192: RISC-V: Merge vector min & max instructs with similar match rules
    • openjdk/jdk#14702 | 8311074: RISC-V: Fix -Wconversion warnings in some code header files
  • Backport jdk17u:

Clang/LLVM RISC-V Porting

You may find more of our code review by searching under the names of the authors above.

gollvm

Awaiting next round of review.

GNU Toolchain

Arch Linux for RISC-V

Gentoo for RISC-V

Stats: 7843/18808, 41.70% (https://whale.plctlab.org/riscv/support-statistics/)

Nixpkgs for RISC-V

Firefox (SpiderMonkey) for RV64GCV

  1. Fixed several sporadic failures, https://phabricator.services.mozilla.com/rELMe75f2469605782e7b784569ddf95024bce6514aa
  2. Enable wasm baseline complier, https://phabricator.services.mozilla.com/D180186

DynamoRIO for RV64GC

This month, we worked predominantly on Box64 and has therefore did not submit any new pull requests. Those that were submitted in May were reviewed and merged.

Up to this point, the basic infrastructures reached preliminary completion. The next step will be working on utility functions for code emit components. In July, we will re-double our effort on DyanoRIO to realise our goal from back in June - running a Hello World program on DynamoRIO.

The following are the aforementioned pull requests:

OpenCV for RISC-V

[WIP] Automated OpenCV Universal Intrinsic code migrator for the RVV backend.

The first patch generated by the code migrator has been accepted by the upstream, opencv/opencv#23885

LIBCXX Experimental/simd

LuaJIT for RV64G

JIT is now largely functional; LuaJIT/LuaJIT-test-cleanup could pass 505/508 cases, on par with LuaJIT on other platform. Programs like Minetest, Scimark, and Sysbench are said to be running without any issues.

There are still some bugs to be fixed, for instance, LuaRocks complains about invalid table metamethods, and NeoVim may segfault while building with a malformed string pointer access.

Additionally, the program doesn't currently have debug information for unwinding. These ought to be fixed soon.

gem5

No update this month.

Spike

QEMU

box64

This month, we continued to improve the dynamic recompiler for the RV64 JIT backend and continued work on library wrappers. We fixed several complicated bugs, added support for more opcodes, and wrapped more libraries and functions (mainly GUI-related).

Another highlight is that we added experimental support for Wine's WoW64 support. With newer Wine versions, you should now be able to run simple 32-bit Windows applications.

Upstreamed pull requests:

Other Supporting Work for RISC-V International

SAIL/ACT

OpenArkCompiler Community

Shi Ninging (史宁宁) continues to work on compiling the OpenArkCompiler Weekly, which just published its 167th issue.

You may find new weekly issues of the OpenArkCompiler Weekly on Sundays on...

MLIR

Upstream Work

Academic Productions

Buddy Compiler

buddy-mlir

Code repository: https://github.com/buddy-compiler/buddy-mlir

buddy-benchmark

Code repository: https://github.com/buddy-compiler/buddy-benchmark

  • Add efficientnet-quantized benchmark.
  • Add validation framework for audio processing cases.
  • Add initial Gemmini benchmark.

Chisel/FIRRTL (CAAT)

coreboot for riscv

No update this month.

openocd

No update this month.

opensbi

u-boot

No update this month.

Aya Theorem Prover

eBPF

RISC-V Platform Evaluation

Following up on last month's updates, we surveyed the effect of common optimization flags on SPEC CPU2017 benchmark results, especially on RISC-V platforms. -flto and -ffast-math were found to be the most commonly used flags (in combination with -O3). Below are the performance uplift we observed on x86:

image

image

image

image

We also tested briefly jemalloc's performance on x86 and RISC-V platforms. While performance gains for memory operations on RISC-V is not significant, on x86, we observed a 25% uplift.

We also explored other flags, see our detailed report.

Here are some updated SPEC CPU2017 figures obtained from Unmatched (GCC 13.1.0, -O3).

image

An error may occur while running 657.xz_s due to memory depletion, as the benchmark requires 16GiB of RAM and Unmatched ships with the same amount.

Testing and Development

Useful Links