v1.9.3

What's Changed

• ✨ Add RISC-V Zicond ISA extension by @stnolting in #743
• [rtl] reset mstatus.mpp to machine-mode by @stnolting in #745
• refine behaviour of CPU sleep signal by @stnolting in #746
• [rtl] minor rtl code cleanups by @stnolting in #747
• [sw] Clean-up software framework by @stnolting in #752
• [rtl] rework FIFO module (to allow inferring block RAM) by @stnolting in #754
• [rtl] minor edits, clean-ups and optimizations; 🔒 set mepc/mtvec/dpc reset value to CPU boot address by @stnolting in #755
• Add GPTMR timer capture by @stnolting in #759
• [rtl] minor code cleanups by @stnolting in #760
• [rtl/core] add again mtime_o to top entity by @mcoroyer in #762
• [rtl] fix minor VHDL coding style issue by @stnolting in #763

New Contributors

• @mcoroyer made their first contribution in #762

Full Changelog: v1.9.2...v1.9.3

v1.9.2

What's Changed

• Fix comment mistake by @Unike267 in #727
• [SPI] re-add high-speed mode by @stnolting in #730
• [XIP] add clock divider for fine-tuning by @stnolting in #731
• 🐛 [FPU] fix wiring of exception flags by @stnolting in #733
• 🐛 fix bug in instruction-misaligned exception handling by @stnolting in #734
• [rtl] cleanup & rework/optimize CPU branch system by @stnolting in #735
• ✨ Add "ASIC style" register file option by @stnolting in #736
• [rtl] Cleanup/update assertions and "auto-configuration" by @stnolting in #738
• Update hardware tigger module (Sdtrig) to version 1.0 by @stnolting in #739
• Add menvcfg[h] CSRs by @stnolting in #741
• [RTE] minor updates by @stnolting in #742

Full Changelog: v1.9.1...v1.9.2

v1.9.1

What's Changed

• Update software framework to gcc-13.2.0 by @stnolting in #705
• [cpu] minor cleanups and optimizations by @stnolting in #707
• ⚠️ remove Zifencei generic - Zifencei ISA extension is now always enabled by @stnolting in #709
• [sw/lib] add nerov32-flavored vprintf funtion by @stnolting in #711
• [sim] Add GHDL run flags variable by @stnolting in #715
• Move FreeRTOS port & demo into new repository by @stnolting in #716
• Fix bug in neorv32_slink_available() function by @Unike267 in #717
• [rtl] cleanups and code beautification by @stnolting in #718
• [sw] update crt0's early-boot trap handler by @stnolting in #719
• [rtl] upgrade neoTRNG to version 3 by @stnolting in #721
• Fix-up the litex wrapper by @Unike267 in #722
• minor rtl code cleanups by @stnolting in #723
• 🧪 provide full hardware reset for all FFs by @stnolting in #724

New Contributors

• @Unike267 made their first contribution in #717

Full Changelog: v1.9.0...v1.9.1

v1.9.0

What's Changed

• minor rtl edits by @stnolting in #684
• Minor rtl edits by @stnolting in #690
• rework watchdog timer and reset system by @stnolting in #692
• implement vectored mtvec by @NikLeberg in #691
• Minor rtl optimizations and cleanups by @stnolting in #694
• [PMP] logic optimization by @stnolting in #695
• [SW] Warning removed of unused variable by @emb4fun in #696
• ⚠️ rework SoC bus protocol by @stnolting in #697
• [SW] Illegal instruction removed by @emb4fun in #698
• [dma] add "transfer done" flag by @stnolting in #699
• Update correct file by @lianakoleva in #702
• minor edits and optimizations by @stnolting in #703
• Match existing filename by @lianakoleva in #704

New Contributors

• @lianakoleva made their first contribution in #702

Full Changelog: v1.8.9...v1.9.0

v1.8.9

What's Changed

• Update RTE to support easy emulation of instructions by @stnolting in #673
• ⚠️ constrain MTVAL CSR, add MTINST CSR by @stnolting in #674
• Add Smcntrpmf ISA extension by @stnolting in #676
• [OCD] add option to select DM legacy mode by @stnolting in #677
• [cpu] remove branch prediction logic by @stnolting in #678
• minor rtl edits and cleanups by @stnolting in #679
• [cpu] add execution monitor by @stnolting in #680
• [CFU] add support for CFU-internal CSRs by @stnolting in #681
• CPU hardware optimization by @stnolting in #683

Full Changelog: v1.8.8...v1.8.9

v1.8.8

What's Changed

• ⚠️ Remove CUSTOM_ID generic by @stnolting in #657
• 🐛 Make sure IMEM/DMEM sizes are a power of two by @stnolting in #658
• ⚠️ Rework SYSINFO module by @stnolting in #659
• [rtl] Cleanups and Optimizations by @stnolting in #660
• ⚠️ Major code edits / cleanups by @stnolting in #664
• [rtl] fix natural condition by @NikLeberg in #665
• minor cleanups by @stnolting in #669
• Remove Zicond ISA extension by @stnolting in #670
• ⚠️ Constrain/optimize MTVAL and MCOUNTEREN CSRs by @stnolting in #671
• [rtl] minor edits and cleanups by @stnolting in #672

Full Changelog: v1.8.7...v1.8.8

v1.8.7

What's Changed

• demo_blink_led_asm bugfix by @vivi202 in #639
• Minor rtl edits, cleanups and optimizations by @stnolting in #641
• Minor rtl edits by @stnolting in #646
• ⚠️ Rework SoC bus system and memory map by @stnolting in #648
• ⚠️ Remove UART sim-mode's 32-bit dump by @stnolting in #650
• ✨ Add support for RISC-V A ISA extension (atomic memory access) by @stnolting in #651
• Minor rtl edits by @stnolting in #652
• [rtl] Optimize bus system and customization options by @stnolting in #653
• 🐛 fixing some LR/SC design flaws by @stnolting in #654

New Contributors

• @vivi202 made their first contribution in #639

Full Changelog: v1.8.6...v1.8.7

v1.8.6

What's Changed

• [TRNG] software can now retrieve FIFO size by @stnolting in #616
• [DMA] add automatic trigger mode by @stnolting in #618
• 🐛 [linker script] fix section continuity issue by @stnolting in #626
• [SYSINFO] re-arrange bits by @stnolting in #627
• ✨ Re-add simplified stream link interface (SLINK) by @stnolting in #628
• ✨ add CRC unit by @stnolting in #632
• [makefile] extend GDB target by @stnolting in #634
• ⚠️ remove BUSKEEPER's status register by @stnolting in #635
• optimize CPU's control logic by @stnolting in #636
• 🧪 VHDL - use entity instantiation by @stnolting in #637

Full Changelog: v1.8.5...v1.8.6

v1.8.5

What's Changed

• ✨ add optional direct memory access controller (DMA) by @stnolting in #593
• [rtl] minor edits by @stnolting in #599
• 🐛 [rtl] fix bug in DMA by @stnolting in #601
• [rtl] minor edits; update to VUnit v5 by @stnolting in #605
• [rtl] rework SoC bus system by @stnolting in #607
• [rtl] minor rtl updates by @stnolting in #608
• 🐛 [FPU] fix bug in FPU trap handling by @stnolting in #609
• [CPU] move instruction address to mtval on ebreak exception by @stnolting in #611
• Add programmable TRNG interrupt by @stnolting in #615

Full Changelog: v1.8.4...v1.8.5

v1.8.4

What's Changed

• [PMP] add support for NA4 and NAPOT modes by @stnolting in #566
• [rtl] cleanups and optimizations by @stnolting in #569
• update XIRQ controller by @stnolting in #570
• [rtl] coding style edits and cleanups by @stnolting in #571
• Remove warnings by @emb4fun in #561
• Updated path for FreeRTOS example - FreeRTOS-Plus-TCP by @matty0005 in #574
• 🐛 FPU bug fix and rtl optimizations by @stnolting in #578
• [UART] add FIFO configuration to DATA register by @stnolting in #581
• 🐛⚠️ CPU bug-fixes, major cleanups and optimizations by @stnolting in #586
• Freertos xirq example by @matty0005 in #585
• [rtl] minor optimizations/cleanups of processor bus system by @stnolting in #591
• Added a test case to show the 1.0 + -1.0 instruction time-out under f… by @mikaelsky in #592

New Contributors

• @matty0005 made their first contribution in #574

Full Changelog: v1.8.3...v1.8.4