v1.7.6

What's Changed

• change base address of BUSKEEPER by @stnolting in #385
• [rtl] relocate TWI tri-state drivers by @stnolting in #386
• [rtl] optimize instruction fetch by @stnolting in #387
• [rtl/PWM] minor cleanup by @stnolting in #388
• 🔒 [TRNG] add read data security feature by @stnolting in #389
• 🚀 [sw] Update software framework to GCC 12.1.0 by @stnolting in #391
• [rtl] minor edits and cleanups by @stnolting in #396
• [sw} cleanup crt0 start-up code by @stnolting in https://github.com//pull/397
• [rtl] core cleanup / minor fixes by @stnolting in #398
• 🚀 [docs] add neorv32-verilog repository by @stnolting in #400

Full Changelog: v1.7.5...v1.7.6

v1.7.5

What's Changed

• 🐛 [rtl] cycle & instret bug fix, wishbone.we bug fix; minor rtl updates by @stnolting in #367
• 🐛 [rtl] fix PMP config by @stnolting in #368
• [rtl] minor edits and updates by @stnolting in #369
• [ug] add new section "LiteX Support" by @stnolting in #370
• 🔒 Specifiy Physical Memory Attributes by @stnolting in #372
• [rtl] add CUSTOM_ID generic by @stnolting in #374
• [sw] add ISR based SPI data flow example by @akaeba in #373
• ⚠️ [linker script] simplify memory configuration by @stnolting in #375
• ⚠️ [rtl] rework SLINK module by @stnolting in #377
• [sw example] demo_spi_irq can handle FIFO by @akaeba in #382
• ✨ [rtl] add optional SPI data FIFO by @stnolting in #381
• [rtl] minor cleanups and optimizations by @stnolting in #383
• [rtl] minor cleanup by @stnolting in #384

Full Changelog: v1.7.4...v1.7.5

v1.7.4

What's Changed

• 🐛 fix CPU stall on illegal LD/ST instruction by @stnolting in #356
• 🧪 [rtl/system_integration] add LiteX core complex wrapper by @stnolting in #353
• [rtl] minor cleanups and typo fixes by @stnolting in #357
• [rtl] add "cached access" infrastructure by @stnolting in #359
• [image_generator, makefile] Update "raw" executable formats by @stnolting in #360
• 🧪 [XIP] add experimental burst mode; fix endianness by @stnolting in #361
• 🐛 [bootloader] fix flash byte-order by @stnolting in #362
• Fix PMP locking by @stnolting in #363
• [sw] update bootloader by @stnolting in #364
• 🐛 [PMP] rework and fixes by @stnolting in #365
• [rtl] reset all "core" CSRs to zero by @stnolting in #366

Full Changelog: v1.7.3...v1.7.4

v1.7.3

What's Changed

• ✨ Add watchdog pause flag by @stnolting in #331
• [rtl] add hardware reset to IO/peripheral devices by @stnolting in #334
• 🐛 fix SPI & XIP clock phase offset by @stnolting in #336
• [rtl] split executable images into package and body by @akaeba in #338
• [rtl] rework TWI module by @stnolting in #340
• [rtl] add Wishbone output "gating" by @stnolting in #344
• [rtl] rework reset system by @stnolting in #345
• ⚠️ [rtl] rework SLINK module by @stnolting in #349
• [rtl] minor clean-ups/optimizations by @stnolting in #351
• [rtl] add "async TX" Wishbone option by @stnolting in #352

New Contributors

• @akaeba made their first contribution in #338

Full Changelog: v1.7.2...v1.7.3

🎉 Two years NEORV32! 😄

v1.7.2

What's Changed

• ⚠️ remove CPU's A ISA extension (atomic memory access) by @stnolting in #308
• Add further mxisa CSR flags by @stnolting in #309
• 🐛 fix bug in CPU counter overflow logic by @stnolting in #310
• update to new neoTRNG v2 by @stnolting in #311
• Cleanup bitmanip co-processor by @stnolting in #312
• 🐛 fix buskeeper timeout error by @stnolting in #315
• [TRNG] add optional/configurable data FIFO by @stnolting in #316
• 🐛 fix XIP sub-word accesses by @stnolting in #320
• crt0.S: Do not clear XIP control registers except in bootloader mode by @jpf91 in #318
• [linker script, crt0] align all sections to 32-bit boundaries by @stnolting in #323
• Constructors by @GideonZ in #324
• 🐛 Fix sync. vs. async. exception collision by @stnolting in #327
• rework bootloader's SPI flash access by @stnolting in #321
• Bugfix - eliminates potential shift of data by 4 bytes. by @GideonZ in #313
• 🐛 fix debugger single-instruction stepping mode by @stnolting in #329

New Contributors

• @jpf91 made their first contribution in #318
• @GideonZ made their first contribution in #324

Full Changelog: v1.7.1...v1.7.2

v1.7.1

What's Changed

• Rework register file's "zero" register by @stnolting in #298
• 🧹 [rtl] CPU frontend cleanup by @stnolting in #299
• [rtl] make CPU front-end synchronous by @stnolting in #300
• [rtl] optimize CPU barrel shifter timing by @stnolting in #301
• VHDL code clean-ups by @stnolting in #303
• Processor check edits by @stnolting in #304
• [rtl] optimize CPU mul/div unit by @stnolting in #305
• ✨ [rtl] add simple branch prediction by @stnolting in #306

ℹ️ See CHANGELOG.md for more details.

Full Changelog: v1.7.0...v1.7.1

v1.7.0

What's Changed

• Fix some typos. by @ahmedcharles in #286
• Fix the link using an asciidoc trick. by @ahmedcharles in #288
• [rtl] set mtval CSR to zero on ebreak instructions by @stnolting in #289
• 🧪 try to fix *_reduce_f functions usage for gate-level simulation by @stnolting in #290
• Typo. by @ahmedcharles in #287
• Move riscv-arch-test tests into separate repository by @stnolting in #291
• rework of CPU's issue engine by @stnolting in #292
• [CPU] area and timing optimization; closing further illegal instruction holes by @stnolting in #293
• [CPU] fixed/optimized (illegal) instruction dcoding logic by @stnolting in #294
• add gate for CSR read address by @stnolting in #295
• Rework C decompressor by @stnolting in #296
• 🐛 fix bug in crt0.S interrupt setup by @stnolting in #297

New Contributors

• @ahmedcharles made their first contribution in #286

Full Changelog: v1.6.9...v1.7.0

v1.6.9

What's Changed

• [rtl/core] rework CPU data path by @stnolting in #279
• 🐛 [rtl/core] fix bug in mip CSR clear/acknowledge by @stnolting in #280
• ⚠️ Rework physical memory protection (PMP) [NAPOT -> TOR] by @stnolting in #281
• Update neorv32_gptmr.c by @prdwivedi in #282
• 🐛 [PMP] fix pmpaddr CSR layout by @stnolting in #283
• [rtl] CPU code clean-up; add RISC-V mstatus.TW CSR bit by @stnolting in #285

ℹ️ See CHANGELOG.md for more details.

New Contributors

• @prdwivedi made their first contribution in #282

Full Changelog: v1.6.8...v1.6.9

v1.6.8

What's Changed

• ✨[Zxcfu ISA ext.] add option to implement custom RISC-V instructions by @stnolting in #264
• 🐛 [sw] fixed bug in bootloader's (M)TIME handling by @stnolting in #267
• 🧪 Using LTO (link-time-optimization) for bootloader + console improvements by @stnolting in #268
• [docs/datasheet] rework & update NEORV32 runtime environment (RTE) section by @stnolting in #272
• [rtl] add err_o signal to IMEM modules by @stnolting in #273
• ✨ [rtl] on-chip debugger: add RISC-V trigger module for hardware breakpoints by @stnolting in #274
• [sw] add support for newlib's system calls by @stnolting in #275
• ⚠️ replace SYSINFO.CPU memory-mapped register by custom "mxisa" CSR by @stnolting in #276
• [OCD] stop CPU counters during debugging by @stnolting in #277
• Add newlib example program and documentation by @stnolting in #278

Full Changelog: v1.6.7...v1.6.8

v1.6.7

What's Changed

• [setups] move to repo neorv32-setups by @umarcor in #254
• [rtl/core] rework CPU issue engine (area optimization) by @stnolting in #256
• [DOC] User Guide - 1.3. Installation by @befedo in #258
• [B ISA extension] add single-bit instructions (Zbs) support by @stnolting in #259
• [B ISA extension] add carry-less multiply instructions (Zbc) support by @stnolting in #260
• [CFS] add demo program by @stnolting in #261
• [rtl/core] add 4 additional CPU CP slots; fix bugs in CP arbitration logic by @stnolting in #262
• [sw] rework intrinsics (e.g. for custom instructions) by @stnolting in #263

New Contributors

• @befedo made their first contribution in #258

Full Changelog: v1.6.6...v1.6.7
Project Changelog: CHANGELOG.md