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adder

Here are 25 public repositories matching this topic...

zslwyuan / Basic-SIMD-Processor-Verilog-Tutorial

Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the fun…

cpu processor simd verilog alu adder instruction-set-architecture cadence-virtuoso multiplier verilog-project processor-design

Updated Jul 17, 2022
Verilog

nxbyte / Verilog-Projects

This repository contains source code for past labs and projects involving FPGA and Verilog based designs

simulator encoder decoder priority verilog xilinx testbenches multiplexer comparator adder system-verilog xilinx-vivado half-adder traffic-light-controller full-adder ripple-adder look-ahead-adder

Updated Oct 2, 2019
Verilog

suoglu / Fixed-Floating-Point-Adder-Multiplier

16-bit Adder Multiplier hardware on Digilent Basys 3

fpga hardware verilog vivado fixed-point floating-point adder multiplier binary16

Updated Aug 3, 2023
Verilog

mongrelgem / Verilog-Adders

Implementing Different Adder Structures in Verilog

verilog hardware-designs adder verilog-hdl verilog-project

Updated Sep 3, 2019
Verilog

sumukhathrey / Verilog_ASIC_Design

Verilog for ASIC Design

counter hardware rtl verilog adder testbench gates sequence-detector hardware-modelling

Updated Sep 13, 2021
Verilog

mattvenn / instrumented_adder

Instrumenting adders to measure speed

asic hardware simulation adder ngspice sky130

Updated Jun 8, 2022
Verilog

KiranThomasCherian / VLSI-and-Computer-Architecture

Computer Architecture -VLSI -Verilog Codes-Xilinx-Irsim

pipeline verilog xilinx floating-point computer-architecture vlsi hardware-modules adder wallace-tree-multiplier iverilog floating-point-arithmetic pipelined carry-propogate-adders kogge-stone-adder sklansky-adder magic-tool gate-layout cmos-path-enumerator

Updated May 8, 2021
Verilog

Performance-Analysis-of-Parallel-Prefix-Adders-Using-Zynq-7000-APSoC

neeraj1397 / Performance-Analysis-of-Parallel-Prefix-Adders-Using-Zynq-7000-APSoC

Performed a comparative study of Parallel Prefix Adders using Verilog HDL on Zynq-7000 APSoC (PL) from XIlinx. Circuits are simulated, synthesized and implemented using Vivado Design Suite.

fpga verilog vivado prefix-tree adder xilinx-fpga xilinx-vivado zynq-7000 han-carlson brent-kung kogge-stone-adder ladner-fischer carry-look-ahead-adder ripple-carry-adder carry-save-adder prefix-adder

Updated Apr 13, 2021
Verilog

sujoyyyy / Computer-Architecture

In computer engineering, computer architecture is a set of rules and methods that describe the functionality, organization, and implementation of computer systems.

verilog floating-point adder single-precision-floating-point

Updated Mar 15, 2021
Verilog

PXVI / std_module

All the fundamental generic verilog modules in one repository. These are fundamentals by my standard, so feel free to suggest more.

encoder decoder rtl mux fifo adder lfsr shifter subtractor verilog-code siso verilog-modules

Updated Oct 20, 2020
Verilog

neelabhro / Complex-Adder-with-SSD

Complex Adder with Seven Segment Display

fsm fpga finite-state-machine adder basys3 seven-segments-display

Updated Apr 24, 2018
Verilog

Zannatul-Naim / Digital-System-Design

Digital System Design Lab Codes using Verilog

verilog adder half-adder d-flipflop full-adder flipflop ripple-carry-adder jk-flipflop t-flipflop

Updated Nov 27, 2022
Verilog

adityagupta1089 / EEP206-Verilog

Verilog Codes for various digital circuits for labs at IIT Ropar, basic gates, adders & subtractors (half & full), ripple adders, multipliers and code converters.

verilog bcd adder digital-circuits gates subtractor ripple-adders multipliers

Updated May 11, 2017
Verilog

Jamboii / verilog-assignments

Source code for various Verilog-based projects and assignments

verilog alu adder combinational-logic

Updated Nov 8, 2018
Verilog

menna15 / Carry-Select-Adder

A carry select adder is an arithmetic combinational logic circuit which adds two N- bit binary numbers and outputs their N-bit binary sum and a 1-bit carry.

verilog adder digital-design logic-design

Updated Aug 9, 2020
Verilog

utkarshad21 / 4-bit-Full-Adder-using-Verilog-HDL

Verilog code and testbench for 4-bit full adder

verilog adder full-adder verilog-project verilog-code 4-bit-adder

Updated Jul 11, 2024
Verilog

sethi-bhumika / FPGA-Design

FPGA design for implementing encoder, adder and counter circuits. (using logic tiles and switch boxes)

counter fpga encoder configurable adder fpga-programming

Updated Nov 27, 2020
Verilog

suoglu / FPAM

Combinational adder and multiplier modules for IEEE 754 single-precision and double-precision floating point format.

fpga floating-point adder multiplier binary32 binary64

Updated Jan 12, 2023
Verilog

SoloSynth1 / 8BitCLA

Verilog for low delay 8-bit CLA with 4-bit lookahead circuits

verilog adder turing-complete carry-look-ahead-adder

Updated Mar 6, 2024
Verilog

newajsharif91 / Verilog_HDL_Digital-System-Design

CSE-2112 Digital Syatem Design LAb

verilog adder flip-flop half-adder d-flipflop full-adder

Updated Jan 20, 2023
Verilog

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