AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
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Updated
Jul 3, 2024 - SystemVerilog
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Common SystemVerilog RTL modules for RgGen
Реализация AXI интерфейса на SystemVerilog
Network on Chip Implementation written in SytemVerilog
Simple single-port AXI memory interface
Synchronous and Asynchronous FIFO with AXI interface
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