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clock-divider

Here are 9 public repositories matching this topic...

arasgungore / VGA-based-screensaver

A VHDL-based VGA driver to implement a square 41x41 screensaver that cycles through 256 different colors.

Updated Aug 8, 2022
VHDL

arasgungore / 256-colors-with-VGA

A VHDL-based VGA driver to display 256 different colors on a monitor.

Updated Aug 8, 2022
VHDL

aybaras / VGA-based-screensaver

A VHDL-based VGA driver to implement a square 41x41 screensaver that cycles through 256 different colors.

Updated Aug 8, 2022
VHDL

JanBurp / MorphaLogic

An eurorack logic module with several logic functions and a clock divider mode. Build around an arduino nano. So could be reprogrammed.

cpp logic logic-gates eurorack flip-flop clock-divider morphagene

Updated Dec 19, 2023
C++

IzyaSoft / EasyHDLLib

A coocbook of HDL (primarily Verilog) modules

fpga verilog altera fifo hdl verilog-hdl xilinx-fpga frequencies frequency-analysis verilog-components verilog-library verilog-snippets clock-divider

Updated Apr 24, 2017
Verilog

suoglu / Verilog-Utilty-Modules

Collection of utility modules written in Verilog

gpio fpga hardware timer random verilog random-number-generators counters fifo pwm clock-divider pulse-width-modulation

Updated Aug 3, 2023
Verilog

HaimOzer123 / Verilog-Clock-Divider-Module---HIT-course---

A Verilog module for generating a divided clock signal with adjustable output frequencies based on a 2-bit input.

hit clock-divider verilog-project

Updated Sep 1, 2024
Verilog

eli-reid / atmega328p_shiftregister

shift register driver for atmega328p it pushes bits down the line making a pwm or clock divider depending on how you use the shift register outputs

atmega shift-register clock-divider 328p serial-parralle

Updated Oct 20, 2019
C

mlab-modules / CLKDIV01

Multiple division ratios can be selected by jumpers. Possible division ratios are: (÷1, ÷2, ÷4, ÷8) or (÷2, ÷4, ÷8, ÷16) every output is synchronous each other. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state.

clock mlab clock-divider mlab-module mlab-clock

Updated Sep 17, 2023

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