Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.
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Updated
Mar 26, 2022 - Verilog
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skywater
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Fully-differential asynchronous non-binary 12-bit SAR-ADC
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Jun 13, 2023 - Verilog
This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specifications, RTL DV, Synthesis, Physical Design, Signoff and Finally Tape-It-Out
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Jan 23, 2024 - Verilog
Mixed-mode silicon cochlea implementing wavelet processing in 130nm skywater process, embedded in efabless Caravel
audio
magic
asic
wavelet
audio-processing
mixed-signal
netgen
integrated-circuits
cochlea
skywater
130nm
switched-capacitor
caravel-shuttle
xshem
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Updated
Sep 24, 2022 - Verilog
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