Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
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Dec 20, 2024 - Python
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systemrdl
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A SystemRDL 2.0 to (synthesizable) SystemVerilog compiler.
asic fpga verilog rdl systemverilog hdl registers systemrdl systemrdl-compiler hardware-description-language register-description-language
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Nov 27, 2021 - Python
SystemRDL lexer for Pygments syntax highlighting
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Dec 14, 2024 - Python
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