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add RAM32X1D inference #33

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wants to merge 43 commits into from
Closed

add RAM32X1D inference #33

wants to merge 43 commits into from

Commits on Oct 23, 2018

  1. xilinx: Add explicit carry techmap for vpr. 

    Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
    @litghost
    litghost committed Oct 23, 2018
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  2. techlibs/xilinx: LUT6 doesn't exist. 

    LUT6 is actually two LUT5s and a MUX.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
    @mithro @litghost
    mithro authored and litghost committed Oct 23, 2018
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  3. Working artix7 carry chains on VPR. 

    Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
    @litghost
    litghost committed Oct 23, 2018
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  4. Adding WIP note.

    @mithro
    mithro committed Oct 23, 2018
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  5. Fix formatting. 

    Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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    litghost committed Oct 23, 2018
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  6. Merge pull request #2 from litghost/xilinx-vpr-carry-chains 

    Working 7-series carry chains on VPR
    @litghost
    litghost authored Oct 23, 2018
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  7. Update DRAM models. 

    Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
    @litghost
    litghost committed Oct 23, 2018
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Commits on Oct 26, 2018

  1. Carry fixes. 

    Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
    @litghost
    litghost committed Oct 26, 2018
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Commits on Nov 2, 2018

  1. Add support for various DRAM modes. 

    Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
    @litghost
    litghost committed Nov 2, 2018
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  2. Rename techmap to ensure order in eblif so that VPR packer works nicely. 

    Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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    litghost committed Nov 2, 2018
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Commits on Nov 3, 2018

  1. Most DRAM modes working. 

    Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
    @litghost
    litghost committed Nov 3, 2018
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  2. Fix assorted errors. 

    Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
    @litghost
    litghost committed Nov 3, 2018
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Commits on Nov 5, 2018

  1. Working sim and add stubs for DRAMs. 

    Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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    litghost committed Nov 5, 2018
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Commits on Nov 16, 2018

  1. Add FF INIT. 

    Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
    @litghost
    litghost committed Nov 16, 2018
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Commits on Nov 19, 2018

  1. Use explicit initial statements for RAMs. 

    Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
    @litghost
    litghost committed Nov 19, 2018
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  2. Remove dead-end models. 

    Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
    @litghost
    litghost committed Nov 19, 2018
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Commits on Dec 19, 2018

  1. Merge pull request #5 from litghost/vpr-dram 

    Changes to support 7-series VPR flow
    @mithro
    mithro authored Dec 19, 2018
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Commits on Feb 7, 2019

  1. Correct map entries for some FF's 

    Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
    @litghost
    litghost committed Feb 7, 2019
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  2. Merge pull request #6 from litghost/correct_map 

    Correct map entries for some FF's
    @mithro
    mithro authored Feb 7, 2019
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Commits on Feb 20, 2019

  1. Added correct techmap for Xilinx 7-series primitives. Modified flow o… 

    …f the "synth_xilinx" macro. Updated manual accordingly.

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
    @mkurc-ant
    mkurc-ant committed Feb 20, 2019
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  2. Refactored techmap definition for Vivado and VPR. Modified "synth_xil… 

    …inx" flow accordingly.

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
    @mkurc-ant
    mkurc-ant committed Feb 20, 2019
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  3. Updated help text in synth_xilinx.cc 

    Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
    @mkurc-ant
    mkurc-ant committed Feb 20, 2019
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  4. Updated reference manual 

    Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
    @mkurc-ant
    mkurc-ant committed Feb 20, 2019
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Commits on Feb 21, 2019

  1. Replaced 4 spaces to tabs. 

    Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
    @mkurc-ant
    mkurc-ant committed Feb 21, 2019
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  2. Unified LUT flow for Vivado and VPR 

    Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
    @mkurc-ant
    mkurc-ant committed Feb 21, 2019
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  3. Merge branch 'master' into master+wip

    @litghost
    litghost committed Feb 21, 2019
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  4. Merge pull request #9 from litghost/update_yosys_with_setundef 

    Update yosys with setundef
    @mithro
    mithro authored Feb 21, 2019
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Commits on Feb 22, 2019

  1. Added negedge sensitive FFs recognized by Vivado, also to the VPR flow. 

    Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
    @mkurc-ant
    mkurc-ant committed Feb 22, 2019
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  2. Merge branch 'fix_reduce_on_ff' into master+wip

    @litghost
    litghost committed Feb 22, 2019
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Commits on Feb 23, 2019

  1. Merge pull request #10 from litghost/master+wip 

    Merge WREDUCE fix to Symbiflow branch
    @litghost
    litghost authored Feb 23, 2019
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Commits on Feb 26, 2019

  1. Merge pull request #8 from antmicro/xilinx_ffmap 

    Moved techmaps from Yosys to SymbiFlow
    @litghost
    litghost authored Feb 26, 2019
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Commits on Feb 28, 2019

  1. Disable RAM32X1D synthesis due to f4pga/f4pga-arch-defs#409 

    Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
    @litghost
    litghost committed Feb 28, 2019
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  2. Merge pull request #11 from litghost/disable_ram32x1d_synthesis 

    Disable RAM32x1D synthesis
    @litghost
    litghost authored Feb 28, 2019
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  3. Merge remote-tracking branch 'yosyshq/master' into master+wip 

    Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
    @litghost
    litghost committed Feb 28, 2019
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  4. Merge pull request #12 from litghost/master+wip 

    Sync with YosysHQ
    @litghost
    litghost authored Feb 28, 2019
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Commits on Mar 1, 2019

  1. Merge pull request #13 from YosysHQ/master 

    merge "YosysHQ/yosys" into master+wip
    @mithro
    mithro authored Mar 1, 2019
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Commits on Mar 5, 2019

  1. Merge yosyshq/master back into master+wip. 

    Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
    @litghost
    litghost committed Mar 5, 2019
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Commits on Mar 6, 2019

  1. Merge pull request #15 from litghost/update_master 

    Merge yosyshq/master back into master+wip.
    @litghost
    litghost authored Mar 6, 2019
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Commits on Mar 7, 2019

  1. Temporarily disable RAMB36 synthesis. 

    Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
    @litghost
    litghost committed Mar 7, 2019
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  2. Merge pull request #16 from litghost/disable_ramb36_until_supported 

    Temporarily disable RAMB36 synthesis.
    @litghost
    litghost authored Mar 7, 2019
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Commits on Mar 14, 2019

  1. Merge branch 'master' into master+wip

    @litghost
    litghost committed Mar 14, 2019
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Commits on Apr 12, 2019

  1. Merge pull request #21 from YosysHQ/master 

    Sync master+wip with upstream
    @litghost
    litghost authored Apr 12, 2019
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Commits on May 10, 2019

  1. add RAM32X1D inference

    @HackerFoo
    HackerFoo committed May 10, 2019
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