Skip to content

Actions: llvm/circt

Actions

Build and Test

Actions

Loading...
Loading

Showing runs from all workflows named Build and Test
10,307 workflow run results
10,307 workflow run results

Filter by Event

Filter by Status

Filter by Branch

Filter by Actor

[Verif] Add LowerFormalToHW pass Build and Test #27420: Pull request #7707 synchronize by leonardt
October 15, 2024 17:00 28m 29s dev/lenny/verif-formal-export-verilog
dev/lenny/verif-formal-export-verilog
October 15, 2024 17:00 28m 29s
[arcilator] Add clock divider integration test Build and Test #27419: Pull request #7705 synchronize by fabianschuiki
October 15, 2024 16:47 33m 23s fschuiki/arc-remove-legalization
fschuiki/arc-remove-legalization
October 15, 2024 16:47 33m 23s
[Arc] Improve LowerState to never produce read-after-write conflicts Build and Test #27417: Pull request #7703 synchronize by fabianschuiki
October 15, 2024 16:45 26m 49s fschuiki/arc-new-lower-state
fschuiki/arc-new-lower-state
October 15, 2024 16:45 26m 49s
[Arc] Remove obsolete arc.clock_tree and arc.passthrough ops Build and Test #27414: Pull request #7704 synchronize by fabianschuiki
October 15, 2024 16:45 30m 32s fschuiki/arc-remove-clock-trees
fschuiki/arc-remove-clock-trees
October 15, 2024 16:45 30m 32s
[arcilator] Add clock divider integration test Build and Test #27415: Pull request #7705 synchronize by fabianschuiki
October 15, 2024 16:45 30m 44s fschuiki/arc-remove-legalization
fschuiki/arc-remove-legalization
October 15, 2024 16:45 30m 44s
[arcilator] Add clock divider integration test Build and Test #27418: Pull request #7705 synchronize by fabianschuiki
October 15, 2024 16:45 26m 36s fschuiki/arc-remove-legalization
fschuiki/arc-remove-legalization
October 15, 2024 16:45 26m 36s
[Arc] Improve LowerState to never produce read-after-write conflicts Build and Test #27416: Pull request #7703 synchronize by fabianschuiki
October 15, 2024 16:45 27m 53s fschuiki/arc-new-lower-state
fschuiki/arc-new-lower-state
October 15, 2024 16:45 27m 53s
[Arc] Add dominance-aware pass to sink ops and merge scf.if ops Build and Test #27412: Pull request #7702 synchronize by fabianschuiki
October 15, 2024 16:45 15m 37s fschuiki/arc-merge-ifs
fschuiki/arc-merge-ifs
October 15, 2024 16:45 15m 37s
[Arc] Remove obsolete arc.clock_tree and arc.passthrough ops Build and Test #27413: Pull request #7704 synchronize by fabianschuiki
October 15, 2024 16:45 14m 45s fschuiki/arc-remove-clock-trees
fschuiki/arc-remove-clock-trees
October 15, 2024 16:45 14m 45s
[Verif] Add LowerFormalToHW pass Build and Test #27411: Pull request #7707 synchronize by leonardt
October 15, 2024 16:22 13m 59s dev/lenny/verif-formal-export-verilog
dev/lenny/verif-formal-export-verilog
October 15, 2024 16:22 13m 59s
[Verif] Add LowerFormalToHW pass Build and Test #27410: Pull request #7707 synchronize by leonardt
October 15, 2024 16:21 13m 56s dev/lenny/verif-formal-export-verilog
dev/lenny/verif-formal-export-verilog
October 15, 2024 16:21 13m 56s
[Verif] Add LowerFormalToHW pass Build and Test #27409: Pull request #7707 synchronize by leonardt
October 15, 2024 16:20 42s dev/lenny/verif-formal-export-verilog
dev/lenny/verif-formal-export-verilog
October 15, 2024 16:20 42s
[Verif] Add LowerFormalToHW pass Build and Test #27408: Pull request #7707 synchronize by leonardt
October 15, 2024 16:10 47s dev/lenny/verif-formal-export-verilog
dev/lenny/verif-formal-export-verilog
October 15, 2024 16:10 47s
[Verif] Add LowerFormalToHW pass Build and Test #27407: Pull request #7707 synchronize by leonardt
October 15, 2024 16:10 43s dev/lenny/verif-formal-export-verilog
dev/lenny/verif-formal-export-verilog
October 15, 2024 16:10 43s
[Verif] Add LowerFormalToHW pass Build and Test #27406: Pull request #7707 synchronize by leonardt
October 15, 2024 16:09 42s dev/lenny/verif-formal-export-verilog
dev/lenny/verif-formal-export-verilog
October 15, 2024 16:09 42s
[Verif] Add LowerFormalToHW pass Build and Test #27405: Pull request #7707 synchronize by leonardt
October 15, 2024 16:02 59s dev/lenny/verif-formal-export-verilog
dev/lenny/verif-formal-export-verilog
October 15, 2024 16:02 59s
[Verif] Add LowerFormalToHW pass Build and Test #27404: Pull request #7707 synchronize by leonardt
October 15, 2024 16:02 45s dev/lenny/verif-formal-export-verilog
dev/lenny/verif-formal-export-verilog
October 15, 2024 16:02 45s
[FIRRTL][ProbesToSignals] RWProbe support (#7706) Build and Test #27403: Commit 5a6a561 pushed by dtzSiFive
October 15, 2024 14:40 15m 14s main
main
October 15, 2024 14:40 15m 14s
[FIRRTL][ProbesToSignals] RWProbe support (#7706) Windows build and test #6681: Commit 5a6a561 pushed by dtzSiFive
October 15, 2024 14:40 13m 54s main
main
October 15, 2024 14:40 13m 54s
[Verif] Add LowerFormalToHW pass Build and Test #27402: Pull request #7707 opened by leonardt
October 15, 2024 00:04 50s dev/lenny/verif-formal-export-verilog
dev/lenny/verif-formal-export-verilog
October 15, 2024 00:04 50s
[arcilator] Add clock divider integration test Build and Test #27401: Pull request #7705 synchronize by fabianschuiki
October 14, 2024 23:35 12m 46s fschuiki/arc-remove-legalization
fschuiki/arc-remove-legalization
October 14, 2024 23:35 12m 46s
[Do not merge][ESI][PyCDE] All necessary changes to support internal BSP Build and Test #27400: Pull request #7695 synchronize by teqdruid
October 14, 2024 23:19 51s teqdruid/esi-channel-map
teqdruid/esi-channel-map
October 14, 2024 23:19 51s
[FIRRTL][ProbesToSignals] RWProbe support Build and Test #27399: Pull request #7706 opened by dtzSiFive
October 14, 2024 21:42 13m 59s dtzSiFive:feature/rwprobe-probestosignals
dtzSiFive:feature/rwprobe-probestosignals
October 14, 2024 21:42 13m 59s
Remove redundant CMakeLists.txt entry (#7696) Windows build and test #6680: Commit dce37cc pushed by leonardt
October 14, 2024 19:33 12m 24s main
main
October 14, 2024 19:33 12m 24s
Remove redundant CMakeLists.txt entry (#7696) Build and Test #27398: Commit dce37cc pushed by leonardt
October 14, 2024 19:33 18m 44s main
main
October 14, 2024 19:33 18m 44s