2022.02

Icicle Kit Reference Design 2022.02

This release moves all DDR in the icicle kit reference design to 64 bit addresses only & is incompatible with previous releases.

Libero version

This release is intended for use with Libero 2021.3.

Pre-built programming files

The Icicle-Kit-2022.02.zip release asset file contains a FlashPro Express programming file including both this Libero FPGA design and Hart Software Services 0.99.29. This programming file can be used to program an Icicle Kit's FPGA and eNVM without having to run through the Libero FPGA flow or building the HSS.

Changes since last release

• Added support for Libero 2021.3.
• Added AXI address shim core to offset addresses from the PCIe block
• Removed unused PCIe LSRAM
• Added core I2C and core UART to the fabric
• Updated core versions in the design
• Disabled MSS QSPI and enabled SPI1 instead
• Added a Linux and bare metal design generation target - this is due to memory map changes in Linux, the only difference in these profiles is the MSS DDR configuration.

2021.11

Icicle Kit Reference Design 2021.11

Libero version

This release is intended for use with Libero 2021.2

Pre-built programming files

The Icicle-Kit-2021.11.zip release asset file contains a FlashPro Express programming file including both this Libero FPGA design and Hart Software Services 0.99.26. This programming file can be used to program an Icicle Kit's FPGA and eNVM without having to run through the Libero FPGA flow or building the HSS.

Changes since the last release

• Added support for Libero 2021.2
• Merged eMMC and SD card scripts
  • There is now one Tcl script called "MPFS_ICICLE_KIT_REFERENCE_DESIGN.tcl" which can be run to generate a reference design
  • eMMC and SD cards are now supported in the same design with XML generated with Libero 2021.2 supporting switching
• Addition of Mi-V Inter Hart Communication (IHC) subsystem
  • This facilitates message sharing between harts / contexts
  • Multiple channels are available consisting of a mailbox and an interrupt aggregator
• Updated accessible range on MSS FICs

2021.08

Icicle Kit Reference Design 2021.08

Libero version

This release is intended for use with Libero 2021.1.

Pre-built programming files

The Icicle-Kit-2021.08.zip release asset file contains a FlashPro Express programming file including both this Libero FPGA design and Hart Software Services 0.99.23. This programming file can be used to program an Icicle Kit's FPGA and eNVM without having to run through the Libero FPGA flow or building the HSS.

Changes since the last release

Support for argument based design generation was added. This allows reconfiguration of the design by passing an argument at generation time. Supported targets include:

• I2C_LOOPBACK: routes both I2C peripherals to I/Os so they can be looped back
• SPI_LOOPBACK: routes both SPI peripherals to I/Os so they can be looped back
• BFM_SIMULATION: generates a SmartDesign test bench which can be used for BFM simulations

Arguments have been added to run the flow and also update the HSS:

• SYNTHESIZE: runs synthesis after generating a design
• PLACEROUTE: runs synthesis and place and route after generating a design
• VERIFYTIMING: runs required steps and timing verification after generating a design
• GENERATE_BITSTREAM: runs required steps and generates files to generate a programming bitstream after generating a design
• PROGRAM: runs the required steps and programs a connected device after generating a design
• EXPORT_FPE: runs the required steps and exports a FlashPro Express programming file after generating a design
• HSS_UPDATE: runs the required steps and downloads and adds the associated HSS release hex file to the Libero project after generating a design

Updated CAN clock frequency in the MSS configuration to 8MHz.

Updated provided XML with the updated CAN clock configuration and added XML for I2C loop back and SPI loop back.

Updated the core voltage setting in the project to 1.05v which requires J45 to be set to the 1.05v position for accurate timing data.

Renamed *_MASTER cores to *_INITIATOR.

Updated the configuration of FIC0_INITIATOR to accommodate PCIe changes by removing PCIe access at address 0x7000_0000 and allowing access only through address 0x20_0000_0000.

Updated the configuration of PCIE_INITIATOR to accommodate PCIe changes to allow access to the 38 bit addressable DDR.

Updated the base design to accommodate PCIe changes by adding gates to act as an address shim and offset addresses from PCIe to 0x10_xxxx_xxxx.

Added a fabric PWM core to FIC3 at address 0x4100_0000 and connected the output to the Mikrobus PWM pin:

• The PWM output is OR'd with the QSPI_DATA3 output
• Note: the PWM core and QSPI peripheral cannot be used simultaneously

Removed unnecessary project saves, design hierarchy builds and tool calls to improve stability and run time.

Moved constraints to the script_support folder.

Resolved warnings generated after running the scripts.

Updated readme and block diagram.

2021.04

Icicle Kit Reference Design Release 2021.04

Changes since last release

This release introduces several updates and additions to the reference design and MSS configuration:

• Added support for Libero 2021.1

• Core names cleaned up to reflect their function instead of the core itself

• Updated cores to the latest versions

• LSRAM usage of the design was reduced

• Added a PF CCC connected to the DRI generating clocks which output to the RPI I/O

• Clock and reset generation was consolidated into a single SmartDesign called “Clocks and Resets”

• Enabled FIC2 and connected it to the 125MHz clock

• Added path length check for Windows and Libero version check for Linux and Windows

• Updated MSS configurator save files and provided XML to 2021.1 format

• Changed MMC voltage level to 1.8V

• Enabled QSPI and connected to MikroBus

• Enabled MMUART4 and connected to MikroBus

• Enabled I2C0 and connected to MikroBus

• Enabled SPI0 and connected to RPI I/O

• L2 cache configuration was updated to allocate:

  • 8 ways to cache
  • 4 ways to L2 LIM
  • 4 ways to scratchpad

• DDR memory partition was updated to allocate:

  • 768MB of cached DDR to 0x8000_0000
  • 256MB of non-cached DDR to 0xC000_0000
  • 1GB of cached DDR to 0x10_0000_0000

Important Notes

• The MMC voltage level change requires jumpers 34 and 43 of the Icicle Kit to be changed from the 1 & 2 position to the 2 & 3 position.

• To fully use the changes in this design ensure you update your embedded software project to use the latest version of MSS configuration description XML file.

2021.02

This release adds support for BFM simulations of the design in Libero SoC with minimal functional changes:

• A SmartDesign test bench is now generated and populated automatically after the reference design has been generated
• 4 of the GPIO outputs of CoreGPIO, at address 0x4200_0000 on FIC 3, are now promoted to the top level and connected to the Raspberry Pi I/O header
• Custom BFM simulation files have been added including commands to simulate this design
• I2C0 has been disabled and constraints removed
• Incorrect interrupt connections were shown in the block diagram and these have been fixed
• Push buttons have been renamed from PBx to SWx+1 in the design and block diagram to match the naming scheme on the Icicle Kit

This release is intended to be used with Libero SoC v12.6.

This tag has been tested to boot using HSS tag 2020.12 and boot Linux, run the Microchip webserver demo and detect USB and PCIe devices using Yocto Linux builds from tag 2021.02.

A FlashPro Express programming file including this design and the HSS tag 2020.12 is available from the assets list below (Icicle-Kit-2021-02.zip).

2020.12

This tag contains several additions and improvements to the Icicle Kit Reference Design since tag 2020.11:

1. Updated to use Libero 12.6
2. Added SDIO control APB register to control SD card/eMMC muxes through fabric logic instead of MSS GPIOs. This requires using HSS 2020.12 or later.
3. Updated the TCL script to copy constraint files instead of linking to them to allow easily copying/archiving the generated Libero design.
4. Added CoreGPIO to the FPGA fabric.

This release is intended to be used with Libero SoC v12.6.

This tag has been tested to boot using HSS tag 2020.12 and boot Linux, run the Microchip webserver demo and detect PCIe devices using Yocto Linux builds from tag 2020.11.

A FlashPro Express programming file including this design and the HSS tag 2020.12 is available from the assets list below (Icicle-Kit-2020.12.zip).

2020.11

This tag contains several additions and improvements to the Icicle Kit Reference Design since tag 2020.10:

1. SPI0 and QSPI have now been disabled, see commit 015dd8

2. CAN0 and CAN1 have now been enabled, see commit 4aef117

3. AXI4_Interconnect_1 slave interface 1 has been updated to have a range of 0x7000_0000 -> 2f_ffff_ffff to allow a greater window for PCIe, see commit ecf2db0

4. A fabric DMA controller was added and connected to FIC0, see commit 08b9aef. A CoreAPB3 and CoreGPIO are now configured but will not be added until Libero SoC v12.6 is released, see commit 00deaf6

5. GPIO connection to SDIO signals:
   The SDIO signals had previously been tied high or low to select eMMC or SD cards, they are now driven by MSS GPIO_2_0. This allows the HSS (from tag 2020.11) to select its boot source by setting the GPIO output. See commit 7e17c9a.

This release is intended to be used with Libero SoC v12.5.

This tag has been tested to boot the HSS using tag 2020.11 and boot Linux, run the Microchip webserver demo and detect PCI devices using Yocto Linux builds from tag 2020.11

2020.10

Tested on PolarFire SoC Icicle Kit with:

• Hart Software Services tag 2020.10
• meta-polarfire-soc-yocto-bsp tag 2020.10

This release is intended to be used with Libero SoC v12.5.