v1.9.4
What's Changed
- [rtl] minor cleanups and optimizations by @stnolting in #764
- [rtl] optimize bus switch by @stnolting in #769
- π Remove RVC float load/store instructions by @stnolting in #771
- β¨ add optional CPU clock gating by @stnolting in #775
- π fix typo that renders the clock gating useless by @stnolting in #776
- [rtl] improve CPU front end by @stnolting in #777
- Updated FIFO NULL assertion fix by @mikaelsky in #778
- set top entiy input defaults to 'L' or 'H' by @stnolting in #779
- π§ͺ extend switchable clock domain by @stnolting in #780
- Fix for issue #782 by @mikaelsky in #783
Full Changelog: v1.9.3...v1.9.4