SPI master and SPI slave for FPGA written in VHDL

An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.

Project for an RPU RISC-V system on chip implementation on the Digilent Arty S7-50 FPGA development board.

Various projects of SPI loader module for xilinx fpga

🌉 A transparent Wishbone-to-SPI bridge supporting Execute-In-Place (XIP).

A Xilinx IP Core and App for line scanner image capture and store

Customizable multi chip select supporting Serial Peripheral Interface master.

IP core for a simple SPI master with variable clock frequncy within AXI peripheral. Developed and tested on Zybo evaluation board (Zynq-7000 product family)

Master SPI Component written in VHDL to control an ADXL345 Accelerometer from a FPGA

SPI Master RTL on fpga. ESP32 was the slave. highly reliable, tested upto 10MHz and 512 bits for transaction length

LED Wall Screen Buffer and Panel Management Controller in VHDL

FPGA Digital Hardware Design

SPI slave mode 0

Nexys 4 DDR - Rom Controller

A Custom AXI4 SPI Peripheral

SPI implementation for FPGA.

VHDL SPI slave, providing Wishbone bus master

This is a digital hardware design of a simple version of SPI communication protocol using VHDL as the HDL.

Analog Digital Three Wire SPI

Development of SPI Slave driver in VHDL and SPI Master driver for STM32 in C along with 8 bit CRC calculation module to ensure data integrity.