v3.4.0-RC1

API Modification

(#1476) Move LFSR16 to Compatibility Mode (Deprecated in 3.2), - Remove deprecated LFSR16 utility
(#1550) Deprecate Module.io and BlackBox.io virtual methods (future 2.13 compatibility)

Fix

(#1425) Report Builder.error errors as exceptions outside hardware context
Some errors that were previously hidden when calling Chisel API methods outside of an active hardware generation context (see #1422) will now be immediately thrown as exception.

(#1426) Fix Double Elaboration Backportably
Fix double elaboration
Expose ChiselStage's PhaseManager, rm extra wraps
Remove the requirement that FirrtlStage runs elaboration (this should
be implicit) and remove the unneeded invalidation of elaboration by
the Emitter. Due to Convert currently NOT invalidating Elaborate (when
it should), add an optionalPrerequisiteOf to ensure that the Emitter
runs before the Convert phase.

(#1480) Fix broken auto-clonetype on Scala 2.11.12 and add test

(#1496) Fix TesterDriver.scala regression #1481

(#1538) Bug fix for manipulating submodules in aspects
Adds functionality for modules' parents to be translated into their corresponding aspect so they can be manipulated in an aspect that injects into the parent module.

(#1546) Counter.n API
Includes special case support for Counter(0) which has identical
behavior to Counter(1) except for the value of n.

(#1534) Add emitSystemVerilog method to ChiselStage
Adds a method for emitting SystemVerilog to the top level API, which previously required a workaround of a few lines of code.

Feature

(#1448) Improved Chisel Naming via Compiler Plugins + Prefixing

(#1499) Basic model checking API
Adds assert(), assume(), cover() statements to a new chisel3.experimental.verification library. These statements generate their FIRRTL counterparts, which in turn emit their Verilog counterparts. Note that only SystemVerilog's immediate statements are supported. These new statements form the foundation of a new model checking interface that may be extended in future releases.

• Add check(...) affordance
• Add assert (renamed from check and fixed)
• Add verification statements
• Move formal to experimental.verification

(#1515) Allow a counter to be instantiated using a Scala range

(#785) Canonicalize construction of Decoupled with no payload

(#1485) Memoize the hashcode of the ChiselCircuitAnnotation, improves performance of multi-phase generators

(#1073) Grouping Chisel API, added a chisel annotation API for triggering the firrtl.transforms.GroupComponents transformation.

(#1203) Add support for ScalaFix.

(#1280) Provide an implementation of litOption() for BundleLits

(#1405) Switch to HowToSerialize for Emission
Fix emit{Firrtl,Verilog} for CustomFileEmission
Change ChiselStage helper methods for emitting FIRRTL (emitFirrtl) and
Verilog (emitVerilog) to look for Circuit and Verilog annotations
instead of DeletedAnnotations. This is needed after migrating to the
CustomFileEmission mixin in FIRRTL where FIRRTL will no longer delete
emitter annotations.

(#1525) update Select.get(IntermediateAnd)Leafs to work with records

(#1527) Allow a counter to be manually reset

(#1420) README: add link to website source. Now easier to figure out how to help enhance the content

(#1518) Check whether signals escape their when scopes
Include and check when scoping as part of reg/mem/wire/node bindings
Allow outdated 'when' behavior of CHIRRTL memory ports with enables
Extend cross-module / when-visibility checks to all data refs

• E.g. delayed evaluation of printf / assert args
• Remove illegal cross-module references from existing tests
  Add basic test cases for cross-module refs / signals escaping when scopes

(#1554) Chisel3 can use treadle to run tests (faster), only depends on Treadle dependency in tests
Makes TesterDriver Backend API extensible, then define a TreadleBackend in the test project

Miscellany

(#1439) Bump 'removed in 3.3' deprecations to 3.4
The removal of unstable methods from chisel3.core from the public API has been delayed. They will be removed with the version 3.4.0 release.

(#1395) Update sbt-site to 1.4.0
(#1413) Update scalacheck-1-14 to 3.1.1.1
(#1415) Update sbt to 1.3.10
(#1429) Update Mergify rules to backport to 3.3.x
(#1430) Update scalatest 3.1.2

(#1459) verilator_4_016 --> v4.016
(#1460) Restore backporting to 3.2.x
(#1479) Have defaultVersions specify complete ModuleIDs.
(#1481) Remove Deprecated Usages of chisel3.Driver, CircuitForm
(#1489) Fix Mergify Backport labeling for 3.2.x
(#1493) Don't run FIRRTL in FlattenSpec's ChiselStage
(#1495) Add .scala-steward.conf
(#1504) fix treadle dependency for mill
(#1511) Update Development Meetings Info
(#1516) Add Treadle to CI builds
(#1524) Update build instructions in README
(#1530) Instance API for Importing Modules
(#1525) Select: update to work with records, Instances work, next need to add plugin
(#1539) Update OneHot.scala
(#1544) Remove ChiselLegacyAnnotation It was private and unused
(#1551) Deprecate support for Scala 2.11
(#1553) Bump Scala to 2.12.12