Chisel v7.0.0-M2

Features

• Add getClassType API to Definition[T <: Class]. (by @mikeurbach in #3877)
  This allows users to get a ClassType for use in other Property types, which is especially useful when constructing aggregate Property types of a specific Class.
• Add suggestName method to HasTarget (by @debs-sifive in #3881)
  HasTarget trait now also exposes suggestName method of a NamedComponent.
• Print the optional Printable passed to stop ops (by @nandor in #3886)
  The message passed to stop is no longer ignored. The construct was extended to accept Printable.
• Add DeletedPath for targets that no longer exist. (by @mikeurbach in #3937)
  Sometimes a generator wants to emit a Path that targets some Data, but that Data isn't always produced by the generator. The DeletedPath can be used to represent the presence of a Path, but the absence of a Data in this case.
• Make firtool options for elaborateGeneratedModule in workspace parametric (by @rameloni in #3952)
  This adds the support in Chiselsim to configure the workspace with additional args for firtool (#3932). The user can specify how the sv circuit is compiled for simulation (i.e. including debug information -g).
• Add a new BoringUtils.drive API for boring to drive a sink. (by @mikeurbach in #3960)
  This API allows users to bore to a sink they plan to drive, which complements the existing API to bore from a source to read.
• Add requireIsAnnotatable for better errors when annotating literals (by @jackkoenig in #3968)
  This gives much better error messages when accidentally dontTouching a literal
• Add extension points on Data for customizing Connectable behavior. (by @mikeurbach in #3978)
  The user can override these methods to customize how their Data applies waive, squeeze, and exclude in its Connectable.
• Add support for generic intrinsic expressions and statements. (by @dtzSiFive in #3986)
  Intrinsic expressions and statements are now supported, streamlining their use. These should be preferred over intrinsicModule's, which in the future will be deprecated and removed.
• make SerializableModuleGenerator work with D/I (by @sequencer in #4003)
• Add Instanitate.definition to get Definition from cache. (by @sequencer in #4020)
• Add private Module API and internal DataMirror API for moduleIOs. (by @mikeurbach in #4036)
  The DataMirror API allows users who know what they're doing to access a module's ports before it is closed.
• [LTL] Added overloadings for AssertProperty (by @dobios in #4037)
• [Formal] Expose Btor2 target (by @dobios in #4035)
  • [Formal] Allow for Chisel to be compiled to btor2 for Bounded Model Checking using ChiselStage.emitBtor2.
• Add modulePorts and fullModulePorts in DataMirror for Instance (by @debs-sifive in #4076)
  Added modulePorts and fullModulePorts methods in DataMirror that returns all ports on an Instance of a module.
• Add .toRelativeTargetToHierarchy (by @mwachs5 in #4067)
  Add .toRelativeTargetToHierarchy for getting .toRelativeTarget functionality when the root is a Definition or Instance.
• Don't ... top of stack trace if it isn't actually trimmed (by @jackkoenig in #4142)
• [LTL] Add support for new sequence and property ops (by @dobios in #4120)
  • [LTL] Add support for intersect, repeat, gotoRepeat, and nonConsecutiveRepeat ops.
• PeekPokeAPI: include source location on failed expect() calls. (by @kivikakk in #4144)
  SimulationData.expect calls now record source location and report it in the FailedExpectationException on failure.
• Preserve literals across .asUInt (by @jackkoenig in #4148)
  This is mostly useful for initial values for async reset registers and for constructing literal values in testing contexts (e.g. ChiselSim). It also should slightly reduce memory use and .fir size.
• Preserve literal value across .asSInt and .zext (by @jackkoenig in #4151)
• Preserve UInt and SInt literals across .pad (by @jackkoenig in #4156)
• Add support for marking things as readOnly (by @jackkoenig in #4190)
  Users can call .readOnly on any Data to prevent connections to the returned value. Resolves #1267.
• Add ChiselStage.emitCHIRRTLFile (by @jackkoenig in #4232)
  Emits a file without returning the serialized object which is more memory efficient and supports > 2 GiB of serialized FIRRTL text.
• Make requireTypeEquivalent public and add context message (by @mwachs5 in #4243)
  Make Add a contextual message to Data.requireTypeEquivalent and expose a public API in DataMirror.requireTypeEquivalent, to make it easier for user code to have good error messages when requiring type equivalence between two chisel Datas
• Add map method for Valid (by @tymcauley in #4255)
  Users can now apply a function f to the bits field of a Valid instance with the new Valid.map(f) method.
• Add more information when probe types don't match (by @mwachs5 in #4269)
  Add more information to the error message when attempting to probe.define to a mismatched chisel type.

API Modification

• Fix tests to avoid inferred width ports on public modules. (by @dtzSiFive in #3869)
  Main module are "public" (#3813, soon mandatory) which means they cannot have inferred widths or abstract resets. Code relying on old behavior will presently encounter an error in firtool.
• Remove circt.Intrinsic annotation. (by @dtzSiFive in #3945)
  IntrinsicModules (intmodule's in FIRRTL) have replaced this entirely for some time now.
• [svsim] Expose further verilator options for trace file name and simulation speed optimization (by @kammoh in #3985)
• Make AssertPropertyLike.createIntrinsic protected (by @jackkoenig in #4058)
  It should never have been a public API
• checkTypeEquivalence now considers ProbeInfo (by @mwachs5 in #4064)
  Now checkTypeEquivalence will check whether data have the same probe type modifier including writeability and color (layer).
• Make "deprecated public" binding APIs private (by @jackkoenig in #4177)
  These chisel3.internal APIs should never have been public in the first place.
• Fix width of ChiselEnum values in emitted FIRRTL (by @jackkoenig in #4200)
  Fixes #4159.
  Previously, the width reported by Chisel under .getWidth was inconsistent with the width of the emitted FIRRTL for ChiselEnum values cast to UInt.
  Temporarily preserve the old behavior under CLI option --use-legacy-width (formerly known as --use-legacy-shift-right-width). Users are encouraged to build Verilog with and without this option enabled and diff the result to verify that this change in width behavior did not silently affect the correctness of their designs.
• Preserve literals across .asTypeOf (by @jackkoenig in #4168)
  Casting a literal (of any type) to another type with .asTypeOf will result in a literal of the new type. For non-literals, the FIRRTL representation will now be a little bit more efficient.
• Intern Width (by @jackkoenig in #4242)
  • UnknownWidth becomes a case object (Drop () when using it).
  • KnownWidths 0-1024 are interned
• SourceInfo: simplify the common case for makeMessage, print it differently (by @mwachs5 in #4249)
  Add a default to SourceInfo.makeMessage() so that users don't always have to write makeMessage(x => x). Change the toString of SourceLine so that it puts a colon instead of a space between the file name and line number, which makes it possible to click-to-source in editors like VSCode.
• Micro-optimize Direction (by @jackkoenig in #4251)
  • Specified and actual direction information are each now stored as single bytes rather than references.
  • This reduces the memory use of a typical bound UInt from 72 bytes shallow, 128 bytes retained to 64 bytes shallow, 120 bytes retained.
  • The change is mostly source compatible, but ActualDirection.Bidirectional, has changed slightly to memoize its two possibilities (Bidirectional.Default and Bidirectional.Flipped). There are deprecations for the typical APIs

API Deprecation

• IntrinsicModule: deprecate in favor of intrinsic expressions. (by @dtzSiFive in #4060)
  IntrinsicModule has been replaced by Intrinsic and IntrinsicExpr ...

Chisel v6.5.0

Features

• Don't ... top of stack trace if it isn't actually trimmed (backport #4142) (by @mergify[bot] in #4143)
• PeekPokeAPI: include source location on failed expect() calls. (backport #4144) (by @mergify[bot] in #4149)
  SimulationData.expect calls now record source location and report it in the FailedExpectationException on failure.
• Preserve literals across .asUInt (backport #4148) (by @mergify[bot] in #4150)
  This is mostly useful for initial values for async reset registers and for constructing literal values in testing contexts (e.g. ChiselSim). It also should slightly reduce memory use and .fir size.
• Preserve literal value across .asSInt and .zext (backport #4151) (by @mergify[bot] in #4152)
• Preserve UInt and SInt literals across .pad (backport #4156) (by @mergify[bot] in #4157)
• Add support for marking things as readOnly (backport #4190) (by @mergify[bot] in #4194)
  Users can call .readOnly on any Data to prevent connections to the returned value. Resolves #1267.
• Add ChiselStage.emitCHIRRTLFile (backport #4232) (by @mergify[bot] in #4234)
  Emits a file without returning the serialized object which is more memory efficient and supports > 2 GiB of serialized FIRRTL text.
• Make requireTypeEquivalent public and add context message (backport #4243) (by @mergify[bot] in #4247)
  Make Add a contextual message to Data.requireTypeEquivalent and expose a public API in DataMirror.requireTypeEquivalent, to make it easier for user code to have good error messages when requiring type equivalence between two chisel Datas
• Add map method for Valid (backport #4255) (by @mergify[bot] in #4258)
  Users can now apply a function f to the bits field of a Valid instance with the new Valid.map(f) method.
• Add more information when probe types don't match (backport #4269) (by @mergify[bot] in #4270)
  Add more information to the error message when attempting to probe.define to a mismatched chisel type.

API Deprecation

• Mark return value of .asTypeOf as "deprecated read-only" (backport #4198) (by @mergify[bot] in #4199)
  Previously, .asTypeOf would return a Wire. To get the old behavior, wrap the .asTypeOf call in WireInit(...).
• [LTL] Deprecate disable intrinsic (backport #4237) (by @mergify[bot] in #4239)

Performance

• Share ChildBinding objects between siblings (backport #4238) (by @mergify[bot] in #4241)
  This reduces memory use by n - 1 times 16-bytes for an Aggregate with n elements.
• Move circuitVar from HasId to BaseModule (backport #4253) (by @mergify[bot] in #4263)
  • This removes a 4-byte field (8-bytes with heap > 32 GB) from all Data
• Optimize Record._elements to not duplicate VectorMap if possible (backport #4254) (by @mergify[bot] in #4265)
  This reduces memory use of a typical bundle by 20%.
• Remove autoSeedVar, use Boolean to distinguish suggested or autoSeed (backport #4252) (by @mergify[bot] in #4262)
  • Combined with #4251, reduces the memory use of a typical bound UInt from 64 bytes shallow, 120 bytes retained, to 56 bytes shallow, 112 bytes retained.
• Optimize .readOnly to only create views when necessary (backport #4271) (by @mergify[bot] in #4273)
• Share Node objects between siblings (backport #4259) (by @mergify[bot] in #4272)
  This reduces memory use by n - 1 times 16-bytes for an Aggregate with n elements.
• Specialize Index for literal indices with LitIndex (backport #4268) (by @mergify[bot] in #4274)
  This saves 16-bytes per Vec element.

Fixes

• Suppress exception throwing in Data.toString (backport #4147) (by @mergify[bot] in #4153)
  This makes .toString behavior better outside of Chisel elaboration contexts.
• Error when calling define targeting a child of a probe (backport #4175) (by @mergify[bot] in #4176)
  This is already an error caught in firtool, now Chisel will error earlier.
• Support XMRs to Analog in D/I (backport #4181) (by @mergify[bot] in #4183)
• Distinguish identity views from single-target views (backport #4186) (by @mergify[bot] in #4189)
  Fixes #4185, Fixes #4187
• Initialize scala.util.control.NonFatal in Builder (backport #4195) (by @mergify[bot] in #4197)
• Fix BoringUtils for identity views (backport #4220) (by @mergify[bot] in #4221)
• Name the targets of identity views (backport #4222) (by @mergify[bot] in #4225)
• Make isView safe outside of Builder context (backport #4228) (by @mergify[bot] in #4231)
• Emit FIRRTL bulk connects even for "input" wires (backport #4219) (by @mergify[bot] in #4235)
• Use :<>= in VecInit methods instead of := or <> (backport #4248) (by @mergify[bot] in #4250)
  Previously, VecInit would try to "intelligently" select := or <> depending on if the type is bidirectional. :<>= has the desirable behavior here for both passive and bidirectional types. It also has the advantage over <> of handling internal wires.
• Fix .toString for dynamic indexing (backport #4260) (by @mergify[bot] in #4267)

Documentation

• Add a test for issue 4159 (backport #4161) (by @mergify[bot] in #4166)
• Add more exhaustive tests for .asTypeOf (backport #4160) (by @mergify[bot] in #4169)
• Fix import path in docstring (backport #4256) (by @mergify[bot] in #4257)

Build and Internal Changes

• [6.x] Enable MiMa for v6.4.0 (by @chiselbot in #4127)

Full Changelog: v6.4.0...v6.5.0

Chisel v3.6.1

Features

• Implement read-write memory accessors for SyncReadMem (backport #3190) (by @mergify[bot] in #3213)
• Allow DataView of Reset <=> [UInt<1>, AsyncReset] (backport #3181) (by @mergify[bot] in #3258)
• Fix color emission to check for interactive terminal (backport #3334) (by @mergify[bot] in #3335)
  • Chisel will now detect when it should print warnings, errors, and deprecations in color.
    • Color can be controlled with environment variable CHISEL_USE_COLOR. Set to true to force Chisel to use color and false to disable it.
    • Due to how the JVM works, detection requires interactive stdout, stderr, and stdin. Build tools like SBT virtualize stdin and thus color will be disabled by default when running a Chisel main with SBT. Detection also requires environment variable TERM to be set to something other than dumb.
• Implement a SyncReadMem wrapper with explicit read, write, and read/write ports (backport #3228) (by @mergify[bot] in #3361)
  This SyncReadMem wrapper is instantiated using a new object, SRAM.apply, and invokes .write, .read, and .readWrite to generate a desired number of read, write, and read/write ports. This function returns a new Bundle wire containing the control signals for each requested port.
• SRAM API: Add a parameter to initialize the memory (backport #3364) (by @mergify[bot] in #3379)
  SRAM.apply and SRAM.masked now take a contents parameter, by default a None, which is a string path to a binary file on the filesystem which the SRAM should be initialized with.
• Support literals and DontCare in DataView targets (backport #3389) (by @mergify[bot] in #3390)
• SRAM API: Add multiple-clocked port API (backport #3383) (by @mergify[bot] in #3404)
  Add new SRAM APIs that take three Clock sequences as parameters instead of the number of read/write/read-write ports. This will sequentially instantiate a memory port for each clock in the Clock sequence and drive them accordingly.
• Add Instance.suggestName (backport #2886) (by @mergify[bot] in #3723)
  Adds suggestName API for hierarchy instances.
• Implement typeName API for stable Module names (backport #3130) (by @mergify[bot] in #4145)
  This gives a flexible way to generate a stable name for a Chisel type, which is useful for problems like generating stable names for Modules and Queues

API Deprecation

• Deprecate calling .viewAs on non-hardware (backport #3395) (by @mergify[bot] in #3399)
  Also fix a crash that could occur when viewing a non-Data containing non-hardware Data.

Backend Code Generation

• Don't emit nodes when calling .asBool on a Bool (backport #3637) (by @mergify[bot] in #3638)
  This results in a slight improvement to emitted FIRRTL quality

Performance

• Optimize BitPat equals, overlap, and cover (backport #3285) (by @mergify[bot] in #3287)
• Convert Vec dynamic index with a literal to static index (backport #3314) (by @mergify[bot] in #3318)
• Fix issue where reify would do the same lookup twice (backport #3392) (by @mergify[bot] in #3396)

Fixes

• Fix Instantiate for Product parameters (backport #3210) (by @mergify[bot] in #3217)
• Don't emit implicit clock warnings for SyncReadMem.readWrite when explicit clocks are used (backport #3313) (by @mergify[bot] in #3315)
• Report Builder errors even when exception is thrown (backport #3341) (by @mergify[bot] in #3342)
  Chisel will to report multiple errors, but this can be cut short by any thrown Exception which would then take precedence over the previously encountered errors. Now Chisel will prioritize reporting errors even if an Exception is thrown.
• Add messages to require statements in Math (backport #3385) (by @mergify[bot] in #3387)
  • log2 functions
    • unsignedBitLength
• Sanitize Record._elements (backport #3419) (by @mergify[bot] in #3426)
  Fixes a bug in D/I where unsanitary names would lead to a crash. It also makes the Printable output for Bundles and Records use the sanitary names which makes them better match the FIRRTL.
• Fix DataMirror.internal.chiselTypeClone to preserve Scala type (backport #3553) (by @mergify[bot] in #3554)
• Fix Decodetable (backport #3563) (by @mergify[bot] in #3579)
• Add type ascription to implicits from instantiable (backport #3615) (by @mergify[bot] in #3617)
  This fixes Scala compiler warnings in Scala 2.13.12 requiring type ascriptions on public implicit definitions.
• Support === on empty Aggregates (backport #3747) (by @mergify[bot] in #3749)
• Fix Reg() to properly handle clocks as rvalues (backport #3775) (by @mergify[bot] in #3778)
  • Clocks are now properly supported by DataView (including FlatIO)
  • Users will also received better error messages when providing invalid clocks to Reg()
• Report source locator in when scoping error messages (backport #3804) (by @mergify[bot] in #3806)
• Fix === for abstract Reset types (backport #3979) (by @mergify[bot] in #3980)
  Previously, the function would infinitely recurse resulting in a stack overflow.
• Fix widths for literal values in Bundle literals (backport #4082) (by @mergify[bot] in #4090)
  Previously, the user-specified (or unspecified minimum width) of the literal would be used in some operations like concatenation. For literal values that are too-wide, they will now truncate to the correct width. This will become a warning (then later an error) in newer major versions of Chisel.

Documentation

• [fix] typo fix: chosen port of arbiter is not onehot but UInt (backport #3235) (by @mergify[bot] in #3260)
  Just a oneline fix to the comment of Arbiter chosen port
• Changed Array to Seq in MuxLookup explantation (backport #3547) (by @mergify[bot] in #3549)
• Update CONTRIBUTING.md (backport #3785) (by @mergify[bot] in #3786)
  Update CONTRIBUTING instructions to clarify backport process and branch to target.
• [website] Update chisel-template repo link to chipsalliance (backport #3871) (by @mergify[bot] in #3894)
• Rename Scala CLI template to example (backport #3917) (by @mergify[bot] in #3918)
  Existing links to https://github.com/chipsalliance/chisel/releases/latest/download/chisel-template.scala should instead use https://github.com/chipsalliance/chisel/releases/latest/download/chisel-example.scala
• Add a test for issue 4159 (backport #4161) (by @mergify[bot] in #4164)

Dependency Updates

• Add Scala 2.13.11 and 2.12.18 to plugin cross versions (backport #3327) (by @mergify[bot] in #3329)
• Add support for Scala 2.13.12 to the compiler plugin (backport #3527) (by @mergify[bot] in #3529)
• Add Scala 2.13.13 to cross-build (backport #3851) (by @mergify[bot] in #3862)
• Add Scala 2.13.14 to cross-build (backport #4044) (by @mergify[bot] in #4045)

Build and Internal Changes

• Read previousVersions for bincompat checking from a file (backport #3202) (by @mergify[bot] in #3207)
• Add workflow to automatically update binary compatibility checks (backport #3242) (by @mergify[bot] in #3249)
• Add new workflow to fixup backports for release notes (backport #3252) (by @mergify[bot] in #3253)
  Improve backport automation so that release notes generation from backport PRs works properly.
• SemanticDB requires private fields of case class to use "val" (backport #3270) (by @mergify[bot] in #3271)
• Fix BuildInfo in 3.6.x (by @sequencer in #3371)
• Update Scala CLI Template (backport #3757) (by @mergify[bot] in #3758)
  • Use "dep" instead of deprecated "lib"
  • Move ChiselStage import above import chisel3._
    • This makes users less likely to run into issues adding import chisel3.util._
  • Bump versions in Github workflows
• Enhance release notes automation (backport #3751) (by @mergify[bot] in #3776)
  • Bump mikepenz/release-changelog-builder-action to v4.1.1
  • It now tabs every line included in the Release Notes section of the PR template
• [ci] Stop copying body over to backports in backport-fixup (backport #4005) (by @mergify[bot] in #4048)
• [3.6.x] Modernize Release Flow (by @jackkoenig in https://g...

Chisel v6.4.0

Features

• [LTL] Added overloadings for AssertProperty (backport #4037) (by @mergify[bot] in #4041)
• Add modulePorts and fullModulePorts in DataMirror for Instance (backport #4076) (by @mergify[bot] in #4077)
  Added modulePorts and fullModulePorts methods in DataMirror that returns all ports on an Instance of a module.

API Modification

• checkTypeEquivalence now considers ProbeInfo (backport #4064) (by @mergify[bot] in #4112)
  Now checkTypeEquivalence will check whether data have the same probe type modifier including writeability and color (layer).

API Deprecation

• Deprecate AssertPropertyLike.createIntrinsic (by @jackkoenig in #4059)
  It should never have been a public API.
• Make it a warning to have too-wide literal values in Bundle Literals (backport #4093) (by @mergify[bot] in #4095)

Fixes

• Fix Nested Instantiate (backport #4018) (by @mergify[bot] in #4027)
  Fix Nested Instantiate
• Fix Typo in ExtractFromVecSizeZero warning message (backport #4029) (by @mergify[bot] in #4031)
• Add support for Vec literals of empty Vecs (backport #4070) (by @mergify[bot] in #4073)
• Fix literal handling for views of empty Aggregates (backport #4071) (by @mergify[bot] in #4075)
  Previously, a view of an empty aggregate would incorrectly always have a litValue of 0.
• Materialize wires for .ref of Aggregate views (backport #4080) (by @mergify[bot] in #4086)
  Fix muxing and probing of views of Aggregates
• [SVSim] Fixed non-firing AssertProperty in SVSim (backport #4087) (by @mergify[bot] in #4089)
  • [SVSim] Fixed AssertProperty failing to fire in verilator simulation.
• Fix widths for literal values in Bundle literals (backport #4082) (by @mergify[bot] in #4092)
  Previously, the user-specified (or unspecified minimum width) of the literal would be used in some operations like concatenation. For literal values that are too-wide, they will now truncate to the correct width. This will become a warning (then later an error) in newer major versions of Chisel.
• BoringUtils: Fix tapAndRead to return same type even when not boring. (backport #4084) (by @mergify[bot] in #4094)
  Always return fully aligned result from tapAndRead, even if no boring performed.
• Don't warn when 0.U used as value for 0-bit BundleLit field (backport #4097) (by @mergify[bot] in #4098)
• Fix boring tap of non-passive source from parent. (backport #4083) (by @mergify[bot] in #4096)
  Fix tapping mix-alignment signal from parent.
• Fix 0 width signals chiselsim (backport #4100) (by @mergify[bot] in #4104)
  Fix failing ChiselSim/SVsim error to simulate modules with zero-width ports.
• Support views of ports in ChiselSim (backport #4107) (by @mergify[bot] in #4110)
  Also fix reifySingleData to return the Data itself if it is not a view.
• FixedIO__Modules with various kinds of probe ports (backport #4105) (by @mergify[bot] in #4111)
  Fix for #4102. Now supported are FlatIO (and therefore FixedIO___Module) of:
  • Probe(Element)
  • Probe(Aggregate)
  • Aggregate(Probes)
  • Aggregates containing any of the above
• Fix svsim with gcc14 (backport #4121) (by @mergify[bot] in #4123)

Dependency Updates

• Add Scala 2.13.14 to cross-build (backport #4044) (by @mergify[bot] in #4047)

Build and Internal Changes

• [6.x] Enable MiMa for v6.3.0 (by @chiselbot in #4017)
• [ci] Stop copying body over to backports in backport-fixup (backport #4005) (by @mergify[bot] in #4043)
• add test for FlatIO port ordering (backport #4113) (by @mergify[bot] in #4115)
  Added a unit test for FlatIO Ordering being maintained
• Bump versions of Github actions to versions using Node 20 (backport #4116) (by @mergify[bot] in #4118)
• Add and use Mill wrapper script (backport #4119) (by @mergify[bot] in #4125)

Full Changelog: v6.3.0...v6.4.0

Chisel v5.3.0

Fixes

• Fix Nested Instantiate (backport #4018) (by @mergify[bot] in #4026)
  Fix Nested Instantiate
• Add support for Vec literals of empty Vecs (backport #4070) (by @mergify[bot] in #4072)
• Fix literal handling for views of empty Aggregates (backport #4071) (by @mergify[bot] in #4074)
  Previously, a view of an empty aggregate would incorrectly always have a litValue of 0.
• [SVSim] Fixed non-firing AssertProperty in SVSim (backport #4087) (by @mergify[bot] in #4088)
  • [SVSim] Fixed AssertProperty failing to fire in verilator simulation.
• Materialize wires for .ref of Aggregate views (backport #4080) (by @mergify[bot] in #4085)
  Fix muxing and probing of views of Aggregates
• Fix widths for literal values in Bundle literals (backport #4082) (by @mergify[bot] in #4091)
  Previously, the user-specified (or unspecified minimum width) of the literal would be used in some operations like concatenation. For literal values that are too-wide, they will now truncate to the correct width. This will become a warning (then later an error) in newer major versions of Chisel.
• Fix 0 width signals chiselsim (backport #4100) (by @mergify[bot] in #4103)
  Fix failing ChiselSim/SVsim error to simulate modules with zero-width ports.
• Fix svsim with gcc14 (backport #4121) (by @mergify[bot] in #4122)

Dependency Updates

• Add Scala 2.13.14 to cross-build (backport #4044) (by @mergify[bot] in #4046)
• Add 2.12.19 to cross-build (by @jackkoenig in #4050)

Build and Internal Changes

• [5.x] Enable MiMa for v5.2.0 (by @chiselbot in #4016)
• [ci] Stop copying body over to backports in backport-fixup (backport #4005) (by @mergify[bot] in #4042)
• add test for FlatIO port ordering (backport #4113) (by @mergify[bot] in #4114)
  Added a unit test for FlatIO Ordering being maintained
• Bump versions of Github actions to versions using Node 20 (backport #4116) (by @mergify[bot] in #4117)
• Add and use Mill wrapper script (backport #4119) (by @mergify[bot] in #4124)

Full Changelog: v5.2.0...v5.3.0

Chisel v5.2.0

Features

• Add Instance.suggestName (backport #2886) (by @mergify[bot] in #3724)
  Adds suggestName API for hierarchy instances.
• Make SRAMInterface parameters publicly available (backport #3826) (by @mergify[bot] in #3827)
  memSize, dataType, numReadPorts, numWritePorts, numReadwritePorts, masked parameters are now visible for SRAMInterface.
• Add requireIsAnnotatable for better errors when annotating literals (backport #3968) (by @mergify[bot] in #3970)
  This gives much better error messages when accidentally dontTouching a literal

Backend Code Generation

• Don't emit nodes when calling .asBool on a Bool (backport #3637) (by @mergify[bot] in #3639)
  This results in a slight improvement to emitted FIRRTL quality

Fixes

• Fix using Definitions as arguments to Definitions (backport #3726) (by @mergify[bot] in #3731)
  Fixes #3708
• Support === on empty Aggregates (backport #3747) (by @mergify[bot] in #3750)
• Fix Reg() to properly handle clocks as rvalues (backport #3775) (by @mergify[bot] in #3779)
  • Clocks are now properly supported by DataView (including FlatIO)
  • Users will also received better error messages when providing invalid clocks to Reg()
• Report source locator in when scoping error messages (backport #3804) (by @mergify[bot] in #3807)
• [svsim] Better error message when verilator not on PATH (backport #3829) (by @mergify[bot] in #3832)
• [svsim] Make EphemeralSimulator multi-processing friendly (backport #3847) (by @mergify[bot] in #3848)
  • Grab a unique temporary directory for every invocation using Java API
  • Allow multiple EphemeralSimulators to run in the same JVM (no longer necessary to single-thread)
  • Use pure Scala code to recursively delete directory at end rather than platform specific rm -rf
• Get ChiselSim working with CIRCT 1.66+ (backport #3890) (by @mergify[bot] in #3891)
• Support serializing large (> 2 GiB) annotation files (backport #3905) (by @mergify[bot] in #3906)
• Fix ChiselStage and Builder handling of logging (backport #3895) (by @mergify[bot] in #3897)
  • Adds support for --log-level to circt.stage.ChiselStage
  • Previously, object circt.stage.ChiselStage was ignoring the Logger.
  • Also, Chisel was not creating its own logger scope which could lead to clobbering of the Console when running invoking Chisel in the same process multiple times.
• toBigInt should round identically for Double and BigDecimal (backport #3921) (by @mergify[bot] in #3926)
• Fix Data.findFirstTypeMismatch to check all elements of Bundles (backport #3928) (by @mergify[bot] in #3929)
  Fixes DataMirror.checkTypeEquivalence to actually check all fields of Bundles and Records. This may expose latent bugs in user code.
• Support literals in DataView (backport #3964) (by @mergify[bot] in #3965)
  View of literals will now themselves be literals. This also fixes an internal bug related to views of literals.
• Fix === for abstract Reset types (backport #3979) (by @mergify[bot] in #3981)
  Previously, the function would infinitely recurse resulting in a stack overflow.
• Provide require message for negative widths (backport #4008) (by @mergify[bot] in #4009)
  Fixes #4007
• Remove extra bit from SRAMInterface address width (backport #3830) (by @mergify[bot] in #3839)

Documentation

• Update CONTRIBUTING.md (backport #3785) (by @mergify[bot] in #3787)
  Update CONTRIBUTING instructions to clarify backport process and branch to target.
• [website] Update chisel-template repo link to chipsalliance (backport #3871) (by @mergify[bot] in #3873)
• Rename Scala CLI template to example (backport #3917) (by @mergify[bot] in #3919)
  Existing links to https://github.com/chipsalliance/chisel/releases/latest/download/chisel-template.scala should instead use https://github.com/chipsalliance/chisel/releases/latest/download/chisel-example.scala

Dependency Updates

• Add Scala 2.13.13 to cross-build (backport #3851) (by @mergify[bot] in #3863)
• Use c++14 to pass the verilator check (backport #3876) (by @mergify[bot] in #3913)
  Change ChiselSim to requires a C++14 compiler.

Build and Internal Changes

• [5.x] Enable MiMa for v5.1.0 (by @chiselbot in #3633)
• Update Scala CLI Template (backport #3757) (by @mergify[bot] in #3759)
  • Use "dep" instead of deprecated "lib"
  • Move ChiselStage import above import chisel3._
    • This makes users less likely to run into issues adding import chisel3.util._
  • Bump versions in Github workflows
• Enhance release notes automation (backport #3751) (by @mergify[bot] in #3777)
  • Bump mikepenz/release-changelog-builder-action to v4.1.1
  • It now tabs every line included in the Release Notes section of the PR template

Full Changelog: v5.1.0...v5.2.0

Chisel v6.3.0

Features

• Add DeletedPath for targets that no longer exist. (backport #3937) (by @mergify[bot] in #3938)
  Sometimes a generator wants to emit a Path that targets some Data, but that Data isn't always produced by the generator. The DeletedPath can be used to represent the presence of a Path, but the absence of a Data in this case.
• Add requireIsAnnotatable for better errors when annotating literals (backport #3968) (by @mergify[bot] in #3971)
  This gives much better error messages when accidentally dontTouching a literal

Performance

• Optimize BitPat factory from UInt literals (backport #3988) (by @mergify[bot] in #3989)
  Speeds up conversion of UInt literals to BitPat by ~9x in practice, ~70x for large UInts.
• Optimize truth table merge (backport #3993) (by @mergify[bot] in #3995)

Fixes

• toBigInt should round identically for Double and BigDecimal (backport #3921) (by @mergify[bot] in #3927)
• Fix Data.findFirstTypeMismatch to check all elements of Bundles (backport #3928) (by @mergify[bot] in #3930)
  Fixes DataMirror.checkTypeEquivalence to actually check all fields of Bundles and Records. This may expose latent bugs in user code.
• Support literals in DataView (backport #3964) (by @mergify[bot] in #3966)
  View of literals will now themselves be literals. This also fixes an internal bug related to views of literals.
• Fix === for abstract Reset types (backport #3979) (by @mergify[bot] in #3982)
  Previously, the function would infinitely recurse resulting in a stack overflow.
• Provide require message for negative widths (backport #4008) (by @mergify[bot] in #4010)
  Fixes #4007

Documentation

• Rename Scala CLI template to example (backport #3917) (by @mergify[bot] in #3920)
  Existing links to https://github.com/chipsalliance/chisel/releases/latest/download/chisel-template.scala should instead use https://github.com/chipsalliance/chisel/releases/latest/download/chisel-example.scala
• [website] Bump Docusaurus to 3.1.1 and fix broken anchors (backport #3948) (by @mergify[bot] in #3949)

Build and Internal Changes

• [6.x] Enable MiMa for v6.2.0 (by @chiselbot in #3915)

Full Changelog: v6.2.0...v6.3.0

Chisel v6.2.0

Features

• Add getClassType API to Definition[T <: Class]. (backport #3877) (by @mergify[bot] in #3879)
  This allows users to get a ClassType for use in other Property types, which is especially useful when constructing aggregate Property types of a specific Class.
• Add suggestName method to HasTarget (backport #3881) (by @mergify[bot] in #3882)
  HasTarget trait now also exposes suggestName method of a NamedComponent.
• Print the optional Printable passed to stop ops (backport #3886) (by @mergify[bot] in #3888)
  The message passed to stop is no longer ignored. The construct was extended to accept Printable.

Fixes

• Get ChiselSim working with CIRCT 1.66+ (backport #3890) (by @mergify[bot] in #3892)
• Support serializing large (> 2 GiB) annotation files (backport #3905) (by @mergify[bot] in #3907)
• Allow BoringUtils.bore to work on probes (backport #3908) (by @mergify[bot] in #3910)
• Fix ChiselStage and Builder handling of logging (backport #3895) (by @mergify[bot] in #3898)
  • Adds support for --log-level to circt.stage.ChiselStage
  • Previously, object circt.stage.ChiselStage was ignoring the Logger.
  • Also, Chisel was not creating its own logger scope which could lead to clobbering of the Console when running invoking Chisel in the same process multiple times.

Documentation

• [website] Update chisel-template repo link to chipsalliance (backport #3871) (by @mergify[bot] in #3874)
• Add explanation for Class and Object, with examples. (backport #3880) (by @mergify[bot] in #3887)

Dependency Updates

• Use c++14 to pass the verilator check (backport #3876) (by @mergify[bot] in #3914)
  Change ChiselSim to requires a C++14 compiler.

Build and Internal Changes

• [6.x] Enable MiMa for v6.1.0 (by @chiselbot in #3867)

Full Changelog: v6.1.0...v6.2.0

Chisel v7.0.0-M1

Features

• Support checking isVisible with reflect.DataMirror (by @poemonsense in #3753)
• Add Layer Colors to Probe Types (by @seldridge in #3744)
• Add DataMirror.getLayerColor (by @seldridge in #3765)
• Provide ImplicitClock and ImplicitReset (by @jackkoenig in #3714)
  These traits implement the functionality formerly only implemented in Module such that they can now be used by RawModules. They also define new protected virtual methods implicitClock and implicitReset that can be overridden within Module to change what values are used as the implicit clock and implicit reset respectively.
• Support isLit for Property types. (by @mikeurbach in #3782)
  Since we override litOption to always be None, we need to override isLit to check the Binding.
• Support isProperty query in DataMirror. (by @mikeurbach in #3783)
  This adds an API to DataMirror to query if a Data is a Property.
• Support Property in BoringUtils. (by @mikeurbach in #3784)
  This adds support for BoringUtils.bore to bore and connect Property ports.
• Add a new DynamicObject.apply method to create Class instances. (by @mikeurbach in #3792)
  This is in addition to the existing support in Definition.apply. Sometimes it is not possible to use Definition.apply, for example, if you plan to bore ports through the Class being constructed. The new DynamicObject.apply method supports this, and creates a DynamicObject from the newly elaborated Class.
• Allow modules to globally enable layers (by @seldridge in #3799)
• Add Public trait to create public FIRRTL modules (by @seldridge in #3813)
• Make SRAMInterface parameters publicly available (by @debs-sifive in #3826)
  memSize, dataType, numReadPorts, numWritePorts, numReadwritePorts, masked parameters are now visible for SRAMInterface.
• Add Property expressions, starting with addition. (by @mikeurbach in #3810)
  This allows Properties to be used to build up expressions in terms of input Properties and literals.
• Add Property expression for integer multiplication. (by @mikeurbach in #3844)
  This adds an API for integer Property multiplication.
• Add Property expression for integer shift right. (by @mikeurbach in #3846)
  This adds an API for integer Property shift right.
• Add DataProduct for Iterables and primitive types (by @jackkoenig in #3856)

API Modification

• Refactor panama binding and converter framwork (by @sequencer in #3754)
• Change the width of static shift right (by @jackkoenig in #3824)
  • A UInt shifted right by a static amount >= its width will now result
    in a 0-bit UInt
  • An SInt shifted right by a static amount >= its width will now result
    in a 1-bit SInt (the sign bit)
    This is a change for SInts which Chisel would treat the output as a 0-bit SInt. However, FIRRTL implemented different behavior where both UInts and SInts would result in 1-bit values (which shifted right by an amount >= the width of the input).
    Users can emulate the old behavior by providing CLI option --use-legacy-shift-right-width. Users are encouraged to generate Verilog with and without this option and diff it to ensure the width change does not affect the correctness of their design. Note that this option is purely for code migration and should not be used long term--it will eventually be removed.
• Bump to firtool-resolver 2.0.0 (by @jackkoenig in #3855)
  This change should be non-breaking for the vast majority of users; however, it does have a substantial impact on Chisel's transitive dependencies which could affect some users. The following transitive dependencies were dropped:
  • com.github.luben:zstd-jni:1.5.5-10
  • com.github.plokhotnyuk.jsoniter-scala::jsoniter-scala-core:2.13.5.2
  • com.lihaoyi::sourcecode:0.3.1
  • com.outr::moduload:1.1.7
  • com.outr::perfolation:1.2.9
  • com.outr::scribe:3.13.0
  • commons-io:commons-io:2.15.0
  • io.get-coursier.jniutils:windows-jni-utils:0.3.3
  • io.get-coursier::coursier-cache:2.1.8
  • io.get-coursier::coursier-core:2.1.8
  • io.get-coursier::coursier-proxy-setup:2.1.8
  • io.get-coursier::coursier-util:2.1.8
  • io.get-coursier::coursier:2.1.8
  • io.github.alexarchambault.windows-ansi:windows-ansi:0.0.5
  • io.github.alexarchambault:concurrent-reference-hash-map:1.1.0
  • javax.inject:javax.inject:1
  • org.apache.commons:commons-compress:1.24.0
  • org.apache.xbean:xbean-reflect:3.7
  • org.codehaus.plexus:plexus-archiver:4.9.0
  • org.codehaus.plexus:plexus-classworlds:2.6.0
  • org.codehaus.plexus:plexus-container-default:2.1.1
  • org.codehaus.plexus:plexus-io:3.4.1
  • org.codehaus.plexus:plexus-utils:4.0.0
  • org.fusesource.jansi:jansi:1.18
  • org.iq80.snappy:snappy:0.4
  • org.slf4j:slf4j-api:1.7.36
  • org.tukaani:xz:1.9
  • org.virtuslab.scala-cli::config:0.2.1
    Any users experiencing issues should consider manually adding whichever of these dependencies they may be relying on.

Backend Code Generation

• Bump to FIRRTL 4.0.0 (by @seldridge in #3803)
• Add format strings to assert and assume (by @uenoku in #3802)
  This supports format strings for assert and assume statements as proposed in chipsalliance/firrtl-spec#166. This change might break existing code if message contains %.

Fixes

• Support === on empty Aggregates (by @jackkoenig in #3747)
• Shift right produce at least 1 bit width result (by @SpriteOvO in #3752)
• Fix Reg() to properly handle clocks as rvalues (by @jackkoenig in #3775)
  • Clocks are now properly supported by DataView (including FlatIO)
  • Users will also received better error messages when providing invalid clocks to Reg()
• Report source locator in when scoping error messages (by @jackkoenig in #3804)
• Fix visibility for views (by @jackkoenig in #3818)
  DataMirror.isVisible and other things checking visibility now work properly for views.
• [svsim] Better error message when verilator not on PATH (by @jackkoenig in #3829)
• Remove extra bit from SRAMInterface address width (by @debs-sifive in #3830)
• [svsim] Make EphemeralSimulator multi-processing friendly (by @jackkoenig in #3847)
  • Grab a unique temporary directory for every invocation using Java API
  • Allow multiple EphemeralSimulators to run in the same JVM (no longer necessary to single-thread)
  • Use pure Scala code to recursively delete directory at end rather than platform specific rm -rf
• Relax legality of defines, align with FIRRTL spec (by @seldridge in #3857)

Documentation

• [docs] Minor updates to README and SETUP for Chisel 6 (by @jackkoenig in #3745)
• [website] Make links more obvious (by @jackkoenig in #3755)
• [website] Write new Installation doc (by @jackkoenig in #3756)
  Revamps the website's instructions for "Getting Started".
• Homebrew sbt for MacOS (by @schoeberl in #3762)
• [docs] Remove SETUP.md in favor of website Installation page (by @jackkoenig in #3764)
• [docs] Make Quickstart instructions more clear (by @jackkoenig in #3774)
• Update CONTRIBUTING.md (by @mwachs5 in #3785)
  Update CONTRIBUTING instructions to clarify backport process and branch to target.
• [docs] Generate ToC for Cookbooks (by @jackkoenig in #3781)
• Add SoC-Now to community projects. (by @shahzaibk23 in #3805)
  Added SoC-Now Framework to community projects.
• [docs] Minor updates to developer docs (by @jackkoenig in #3815)
• [docs] Update Connectable explanation (by @tymcauley in #3664)

Dependency Updates

• [cd] Bump CIRCT from firtool-1.62.0 to firtool-1.63.0 (by @chiselbot in #3760)
• [cd] Bump CIRCT from firtool-1.63.0 to firtool-1.64.0 (by @chiselbot in #3800)
• [cd] Bump CIRCT from firtool-1.64.0 to firtool-1.65.0 (by @chiselbot in #3811)
• [cd] Bump CIRCT from firtool-1.65.0 to firtool-1.66.0 (by @chiselbot in #3831)
• de-bump to sbt 1.9.7 (by @debs-sifive in #3852)
  De-bumping to sbt 1.9.7 to avoid glibc issues for users, manifesting as:

  java.lang.UnsatisfiedLinkError: ...
  

Chisel v6.1.0

Features

• Support checking isVisible with reflect.DataMirror (by @poemonsense in #3753)
• Provide ImplicitClock and ImplicitReset (backport #3714) (by @mergify[bot] in #3769)
  These traits implement the functionality formerly only implemented in Module such that they can now be used by RawModules. They also define new protected virtual methods implicitClock and implicitReset that can be overridden within Module to change what values are used as the implicit clock and implicit reset respectively.
• Support isLit for Property types. (backport #3782) (by @mergify[bot] in #3789)
  Since we override litOption to always be None, we need to override isLit to check the Binding.
• Support isProperty query in DataMirror. (backport #3783) (by @mergify[bot] in #3790)
  This adds an API to DataMirror to query if a Data is a Property.
• Support Property in BoringUtils. (backport #3784) (by @mergify[bot] in #3791)
  This adds support for BoringUtils.bore to bore and connect Property ports.
• Add a new DynamicObject.apply method to create Class instances. (backport #3792) (by @mergify[bot] in #3797)
  This is in addition to the existing support in Definition.apply. Sometimes it is not possible to use Definition.apply, for example, if you plan to bore ports through the Class being constructed. The new DynamicObject.apply method supports this, and creates a DynamicObject from the newly elaborated Class.
• Make SRAMInterface parameters publicly available (backport #3826) (by @mergify[bot] in #3828)
  memSize, dataType, numReadPorts, numWritePorts, numReadwritePorts, masked parameters are now visible for SRAMInterface.
• Add Property expressions, starting with addition. (backport #3810) (by @mergify[bot] in #3843)
  This allows Properties to be used to build up expressions in terms of input Properties and literals.
• Add Property expression for integer multiplication. (backport #3844) (by @mergify[bot] in #3845)
  This adds an API for integer Property multiplication.
• Add Property expression for integer shift right. (backport #3846) (by @mergify[bot] in #3850)
  This adds an API for integer Property shift right.
• Add DataProduct for Iterables and primitive types (backport #3856) (by @mergify[bot] in #3860)

Fixes

• Support === on empty Aggregates (by @jackkoenig in #3747)
• Fix Reg() to properly handle clocks as rvalues (backport #3775) (by @mergify[bot] in #3780)
  • Clocks are now properly supported by DataView (including FlatIO)
  • Users will also received better error messages when providing invalid clocks to Reg()
• Report source locator in when scoping error messages (backport #3804) (by @mergify[bot] in #3808)
• Fix visibility for views (backport #3818) (by @mergify[bot] in #3821)
  DataMirror.isVisible and other things checking visibility now work properly for views.
• [svsim] Better error message when verilator not on PATH (backport #3829) (by @mergify[bot] in #3833)
• Remove extra bit from SRAMInterface address width (backport #3830) (by @mergify[bot] in #3840)
• [svsim] Make EphemeralSimulator multi-processing friendly (backport #3847) (by @mergify[bot] in #3849)
  • Grab a unique temporary directory for every invocation using Java API
  • Allow multiple EphemeralSimulators to run in the same JVM (no longer necessary to single-thread)
  • Use pure Scala code to recursively delete directory at end rather than platform specific rm -rf

Documentation

• [docs] Minor updates to README and SETUP for Chisel 6 (by @jackkoenig in #3745)
• Update CONTRIBUTING.md (backport #3785) (by @mergify[bot] in #3788)
  Update CONTRIBUTING instructions to clarify backport process and branch to target.

Dependency Updates

• de-bump to sbt 1.9.7 (backport #3852) (by @mergify[bot] in #3854)
  De-bumping to sbt 1.9.7 to avoid glibc issues for users, manifesting as:

  java.lang.UnsatisfiedLinkError: Error looking up function 'stat': java: undefined symbol: stat
  

• Add Scala 2.13.13 to cross-build (backport #3851) (by @mergify[bot] in #3864)

Build and Internal Changes

• [main] Enable MiMa for v6.0.0 (by @chiselbot in #3743)
• Enhance release notes automation (by @jackkoenig in #3751)
  • Bump mikepenz/release-changelog-builder-action to v4.1.1
  • It now tabs every line included in the Release Notes section of the PR template
• Update Scala CLI Template (backport #3757) (by @mergify[bot] in #3861)
  • Use "dep" instead of deprecated "lib"
  • Move ChiselStage import above import chisel3._
    • This makes users less likely to run into issues adding import chisel3.util._
  • Bump versions in Github workflows

Full Changelog: v6.0.0...v6.1.0