Blaster

Overview

Sayma RTM is designed to operate at DAC clock speeds up to 2.4 GSPS, allowing the direct synthesis of digitally modulated tones out to ~3.4 GHz (in the third Nyquist zone), with higher frequencies accessible using an analog upconversion stage. For applications in superconducting qubits, where typical frequencies are in the 4-10 GHz range, it would be advantageous to have the ability to perform direct synthesis with pulse shaping/modulation done in the digital domain.

Analog Devices has come out with a new set of chips (AD916x) which support output update rates of 12 GSPS, with instantaneous bandwidths of >1 GHz and a variety of interpolation factors. These are suitable for direct synthesis of signals with frequencies up to ~9-10 GHz (depending on how much power one needs) using mix mode, same principle as the AD9154. These capabilities would allow fully digital modulation and direct output of shaped/modulated signals with frequencies and bandwidths relevant for superconducting qubit experiments. The phase noise performance is somewhat better than that of the AD9154 as well. This could be a huge boon for scaling sc qubit systems, as it would dramatically reduce the physical size and complexity of the classical control infrastructure (no more external modulators, fewer filters, no more bulky generators, etc).

One could fit 4 single-channel DACs on a new RTM board (4 lanes each at 10 Gbps gives 1 GHz instantaneous bandwidth, use 6x interpolation, 6 GHz DAC clock, 12 GSPS output update) for use with the existing Sayma AMC. Resource usage on the AMC FPGA should be similar (~double the data rate per channel but half the number of channels). One could also add an ADC if desired, e.g. a 500 MSPS 4-channel ADC (e.g. AD9694) for qubit readout signals (this would still require an external demodulation circuit).

Another alternative would be to use RFSoCs which have been announced by Xilinx, which contain DACs and ADCs integrated directly on chip with the FPGA fabric. Full performance specifications are not yet known, but these have the potential to dramatically simplify board layout and reduce latency for feedback operations.

Some groups might prefer a card with fast parallel DACs (e.g. LTC2000) followed by analog modulation on an analog front end (AFE) card with surface-mount modulators/mixers. Coupled with fast parallel ADCs and analog demodulation on the AFE, this would provide very low latency for feedback operations, at the cost of performing some of the desired modulation in the analog domain.

Further discussion took place in issue #183

Status

This project is not funded and a specification has not been finalized. Input is desired from interested groups.

Desired performance/specifications

• Frequencies - generally 4-10 GHz should cover the desired range. Some users may be satisfied with 4-8 GHz.
• Instantaneous bandwidth - 1 GHz is the minimum number one should shoot for, higher is better.
• Latency - as low as possible for feedback applications. For comparison, the state of the art from Zurich Instruments offers approximately 1.1 us loop time from the start of a readout pulse being digitized to the start of a feedback pulse being emitted at the analog front end. Given that integration times for the signal are ~300 ns, any design should aim for ~700 ns or better total latency, including ADC, FPGA decision/logic, and DAC latencies. This may be challenging with JESD204B.
• Resolution - many groups are happy with 10-bit resolution, 12-bit or 14-bit would be nice, 16-bit is probably overkill but if it's available with equivalent other parameters (latency/bandwidth/frequency) it might be nice to have the additional resolution.
• Clock - a high-quality clock will be required for high-fidelity operations. Probably a clock mezzanine on the RTM is desirable, along with an HMC830 to generate the desired clock from backplane clocks if preferred. Front panel SMA for external clock should also be available.
• ADC - most likely an ADC will be desired to allow for fast feedback to the DAC outputs based on an analog input signal from a qubit measurement pulse. This could be either a JESD204B model or a parallel model, depending on the desired latency to be achieved. ADC can have lower resolution, 8-10 bits is probably sufficient, especially if resolution can be traded for increased speed/reduced latency.
• AMC card - For JESD204B DACs and ADCs, this could use the Sayma AMC as a front card. If DACs and ADCs use parallel data buses, it might be better to put an FPGA on the RTM card and use a "dumb" AMC card adapter to connect the RTM card directly to the AMC backplane (as proposed as one variant in Shuttler design).
• FPGA - for fast feedback, it may be preferable to put an FPGA on the RTM card to interface directly with the DAC and ADC (similar to proposed Shuttler design). This would be the design modality of choice for ultra-low latency and if parallel (as opposed to JESD204) DAC/ADC chips are to be used.
• Analog front ends - depending on choice of DAC/ADC, these would either be simple amplification/filtering stages or contain up/down-converting stages. We should decide whether to maintain pin-compatible form-factor with Sayma RTM -- this should only be done if voltages/ranges on DAC/ADC are compatible with those on Sayma RTM, but could allow for design/board reuse, which would be helpful. In particular, the Allaki front end can potentially run up to higher frequencies than Sayma can source, but which might be directly synthesized from Blaster.